Patents by Inventor Po-Kai Hou

Po-Kai Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240077543
    Abstract: A battery pack includes a group of cells, a current path switch coupled to the group of cells, and a current monitoring system. The current monitoring system includes a signal detection unit, a logic unit and a current path control unit. The signal detection unit is coupled to the group of cells and/or a positive terminal of the battery pack, and used to detect at least one voltage signal of the group of cells and/or of the positive terminal of the battery pack. The logic unit is coupled to the signal detection unit, and used to generate a calculated value of a voltage signal of the at least one voltage signal and generate a logic signal according to the calculated value. The current path control unit is coupled to the logic unit and the current path switch, and used to control the current path switch according to the logic signal.
    Type: Application
    Filed: April 10, 2023
    Publication date: March 7, 2024
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: Hsu-Kai Hou, Po-Ching Lee, Tseng-Chuan Wu
  • Patent number: 7842550
    Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 30, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Chun-Ying Lin, Geng-Shin Shen, Po-Kai Hou
  • Patent number: 7812432
    Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: October 12, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Po-Kai Hou, Chi-Jin Shih
  • Publication number: 20100120201
    Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.
    Type: Application
    Filed: December 11, 2008
    Publication date: May 13, 2010
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Chun-Ying Lin, Geng-Shin Shen, Po-Kai Hou
  • Publication number: 20090321988
    Abstract: In a chip packaging process, an upper and a lower mold chases are provided. A thickness adjusting film is then provided below the upper mold chase and/or above the lower mold chase. Next, a carrier is delivered to a position between the upper and the lower mold chases. A chip and a conductive line are disposed on the carrier, and the thickness adjusting film is located between the upper mold chase and the carrier and/or between the lower mold chase and the carrier. The upper and the lower mold chases are attached to define a cavity, and the thickness adjusting film is located on the surface of the upper mold chase and/or the surface of the lower mold chase. Thereafter, a molding compound is provided into the cavity by using a molding compound supplying unit. The upper and the lower mold chases and the thickness adjusting film are removed.
    Type: Application
    Filed: September 8, 2009
    Publication date: December 31, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: Po-Kai Hou
  • Publication number: 20090224384
    Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.
    Type: Application
    Filed: November 11, 2008
    Publication date: September 10, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Po-Kai Hou, Chi-Jin Shih
  • Publication number: 20090206519
    Abstract: A chip packaging apparatus including an upper mold chase, a lower mold chase, a carrier delivering unit, a molding compound thickness adjusting unit, and a molding compound supplying unit is provided. The lower mold chase is disposed below the upper mold chase. The carrier delivering unit delivers a carrier to a position between the upper mold chase and the lower mold chase. The molding compound thickness adjusting unit provides a thickness adjusting film between the upper mold chase and the carrier and/or between the lower mold chase and the carrier, and adjusts the thickness of the molding compound according to the thickness of the thickness adjusting film. The molding compound supplying unit is connected to the upper mold chase or the lower mold chase for providing the molding compound into a cavity defined by the upper mold chase and the lower mold chase.
    Type: Application
    Filed: November 10, 2008
    Publication date: August 20, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: Po-Kai Hou
  • Publication number: 20090127684
    Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, an insulating layer, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The insulating layer is filled in a plurality of slots between the package areas. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 21, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HENG CHANG KUO, PO KAI HOU, CHUN YING LIN
  • Publication number: 20090108424
    Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of first slots, a plurality of first side rails, a plurality of second side rails, and tape. Each of the package areas comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of first side rails and the plurality of second side rails are connected and surround the plurality of the package areas. The tape fixes the plurality of package areas, the plurality of first side rails, the plurality of second side rails, the die pads, and the plurality of leads in place.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 30, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HENG CHANG KUO, PO KAI HOU, CHUN YING LIN
  • Publication number: 20090108419
    Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, a plurality of connection portions, a plurality of openings, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The plurality of connection portions connect the plurality of package areas. The plurality of openings are disposed on the plurality of connection portions, and are aligned with some of the plurality of slots. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 30, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HENG CHANG KUO, PO KAI HOU, CHUN YING LIN