Patents by Inventor Po-Kai Hsiao

Po-Kai Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378261
    Abstract: In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Hsuan-Hsiao Yao, Po-Kai Hsiao, Fan-Cheng Lin, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230326802
    Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 12, 2023
    Inventors: Szu-Chi Yang, Allen Chien, Tsai-Yu Huang, Chien-Chih Lin, Po-Kai Hsiao, Shih-Hao Lin, Chien-Chih Lee, Chih Chieh Yeh, Cheng-Ting Ding, Tsung-Hung Lee
  • Publication number: 20230326788
    Abstract: A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fan-Cheng LIN, Po-Kai HSIAO, Tsai-Yu HUANG, Huicheng CHANG, Yee-Chia YEO
  • Publication number: 20230274972
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.
    Type: Application
    Filed: May 8, 2023
    Publication date: August 31, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Kai HSIAO, Tsai-Yu HUANG, Hui-Cheng CHANG, Yee-Chia YEO
  • Patent number: 11688625
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Kai Hsiao, Tsai-Yu Huang, Hui-Cheng Chang, Yee-Chia Yeo
  • Patent number: 11670551
    Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
  • Publication number: 20230068951
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Kai HSIAO, Tsai-Yu HUANG, Hui-Cheng CHANG, Yee-Chia YEO
  • Publication number: 20220230908
    Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Po-Kai Hsiao, Han-De Chen, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20210098305
    Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
    Type: Application
    Filed: July 10, 2020
    Publication date: April 1, 2021
    Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
  • Patent number: 9893185
    Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ta Wu, Yu-Ting Lin, Po-Kai Hsiao, Po-Kang Ho, Ting-Chun Wang
  • Publication number: 20170250282
    Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Inventors: Cheng-Ta Wu, Yu-Ting Lin, Po-Kai Hsiao, Po-Kang Ho, Ting-Chun Wang