Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A dielectric grating apparatus comprises a substrate; a grating layer, disposed above the substrate; a first interference layer, disposed above the substrate; and a second interference layer, adjacent to the first interference layer, wherein a refractive index of a material of the second interference layer is greater than a refractive index of a material of the first interference layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: The disclosure provides a fixing assembly adapted to fix an expansion card on an expansion slot of a motherboard. The fixing assembly includes a casing, a first positioning component and a second positioning component. The first positioning component is slidably disposed on the casing so that a distance between the first positioning component and the expansion slot of the motherboard is adjustable. The second positioning component is slidably disposed on the first positioning component. The second positioning component and the first positioning component are configured to press against the expansion card, and sliding directions of the first positioning component and the second positioning component are different from each other.

Abstract: The disclosure provides a fixing assembly adapted to fix an expansion card on an expansion slot of a motherboard. The fixing assembly includes a casing, a first positioning component and a second positioning component. The first positioning component is slidably disposed on the casing so that a distance between the first positioning component and the expansion slot of the motherboard is adjustable. The second positioning component is slidably disposed on the first positioning component. The second positioning component and the first positioning component are configured to press against the expansion card, and sliding directions of the first positioning component and the second positioning component are different from each other.

Abstract: A multi-directional fiber optic connector includes a housing defining therein a mating-connection chamber, a mating-connection portion having an insertion hole in communication with the accommodation chamber and a plurality of guide grooves equiangularly spaced around the insertion hole for guiding a fiber optic lead end connector of a fiber optic cable into the insertion hole in one of a series of angular positions and an accommodation chamber located at an opposite side of said mating-connection chamber, said mating-connection portion comprising, and an optical device mounted in the accommodation chamber for optical communication with the inserted fiber optic cable.

Abstract: A light-shielding fiber optic connector includes a housing defining therein a mating-connection chamber, a mating-connection portion at one side of the mating-connection chamber, an accommodation chamber at an opposite side of the mating-connection chamber and a plug hole perpendicularly connected to the mating-connection chamber, an optical device mounted in the accommodation chamber with a light source transceiver thereof facing toward the mating-connection chamber, a light-shielding device mounted in the plug hole and providing a flexible light-shielding portion for blocking between the mating-connection chamber and the accommodation chamber to prevent light leakage and to prohibit external dust from contaminating the optical device, and a position-limiting member mounted to the housing to hold down the light-shielding device in the plug hole.

Abstract: A multi-directional fiber optic connector includes a housing defining therein a mating-connection chamber, a mating-connection portion having an insertion hole in communication with the accommodation chamber and a plurality of guide grooves equiangularly spaced around the insertion hole for guiding a fiber optic lead end connector of a fiber optic cable into the insertion hole in one of a series of angular positions and an accommodation chamber located at an opposite side of said mating-connection chamber, said mating-connection portion comprising, and an optical device mounted in the accommodation chamber for optical communication with the inserted fiber optic cable.

Abstract: A display panel includes an array substrate, an opposite substrate, and at least one closed sealing element. The array substrate has a first through hole, and the array substrate includes a plurality of pixel units, a plurality of scan lines, and a plurality of data lines. The scan lines are electrically connected to the pixel units. The data lines intersect with the scan lines, and the data lines are electrically connected to the corresponding pixel units. The opposite substrate is disposed opposite to the array substrate, and the opposite substrate has a second through hole. The closed sealing element is disposed between the array substrate and the opposite substrate, and the closed sealing element has a third through hole. The first through hole, the second through hole, and the third through hole form an opening.

Abstract: A display panel includes an array substrate, an opposite substrate, and at least one closed sealing element. The array substrate has a first through hole, and the array substrate includes a plurality of pixel units, a plurality of scan lines, and a plurality of data lines. The scan lines are electrically connected to the pixel units. The data lines intersect with the scan lines, and the data lines are electrically connected to the corresponding pixel units. The opposite substrate is disposed opposite to the array substrate, and the opposite substrate has a second through hole. The closed sealing element is disposed between the array substrate and the opposite substrate, and the closed sealing element has a third through hole. The first through hole, the second through hole, and the third through hole form an opening.

Abstract: A gate-on array shift register includes a signal-input unit, a control transistor and at least three stable modules. The signal-input unit receives and outputs a previous-stage output signal. The control terminal of the control transistor is electrically coupled to the signal-input unit for receiving the previous-stage output signal. The control transistor outputs corresponding output signal on output terminal of the shift register according to the previous-stage output signal. Each of the stable modules is electrically coupled to the control terminal of the control transistor and the output terminal of the shift register to stabilize voltage of the terminals.

Abstract: A gate-on array shift register includes a signal-input unit, a control transistor and at least three stable modules. The signal-input unit receives and outputs a previous-stage output signal. The control terminal of the control transistor is electrically coupled to the signal-input unit for receiving the previous-stage output signal. The control transistor outputs corresponding output signal on output terminal of the shift register according to the previous-stage output signal. Each of the stable modules is electrically coupled to the control terminal of the control transistor and the output terminal of the shift register to stabilize voltage of the terminals.