Patents by Inventor Po-Liang Yeh

Po-Liang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367795
    Abstract: A semiconductor device including a first substrate and a thin film transistor disposed on the first substrate is provided. The thin film transistor includes a gate, a semiconductor pattern, a first insulating layer, a source and a drain. The first insulating layer is disposed between the gate and the semiconductor pattern. The source and the drain are separated from each other and disposed corresponding to the semiconductor pattern. At least one of the source and the drain has a first copper patterned layer and a first copper oxynitride patterned layer. The first copper oxynitride patterned layer covers the first copper patterned layer. The first copper patterned layer is disposed between the first copper oxynitride patterned layer and the first substrate. Moreover, a manufacturing method of the semiconductor device is also provided.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: June 21, 2022
    Assignee: Au Optronics Corporation
    Inventors: Ting-Fong Chien, Po-Liang Yeh, Chen-Chung Wu, Chia-Ming Chang, Chun-An Chang
  • Publication number: 20210367079
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided: forming a first metal layer on a substrate; forming an insulating layer on the first metal layer; forming an oxide semiconductor material layer on the insulating layer; performing an annealing treatment to the oxide semiconductor material layer; forming an etch stopping material layer on the oxide semiconductor material layer; forming a photoresist material layer on the etch stopping material layer and defining thereof with a half tone photomask to form a photoresist pattern; using the photoresist pattern as a mask, patterning the etch stopping material layer to form an etch stopping pattern, and patterning the oxide semiconductor material layer to form an oxide semiconductor layer; removing the photoresist pattern; using the etch stopping pattern as the mask, patterning the insulating layer; forming a second metal layer on the etch stopping pattern; and patterning the oxide semiconductor layer.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Patent number: 11171244
    Abstract: A semiconductor structure disposed on a substrate including a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopping pattern disposed on the oxide semiconductor layer, and a second metal layer disposed on the etch stopping layer. The first metal layer includes a gate line. The gate insulating layer covers the gate line. Patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern. The etch stopping layer is located between the second metal layer and the oxide semiconductor layer. The second metal layer includes a signal line disposed on the etch stopping layer and is electrically connected to the oxide semiconductor pattern. A manufacturing method of the semiconductor structure is also provided.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: November 9, 2021
    Assignee: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Publication number: 20210050454
    Abstract: A semiconductor device including a first substrate and a thin film transistor disposed on the first substrate is provided. The thin film transistor includes a gate, a semiconductor pattern, a first insulating layer, a source and a drain. The first insulating layer is disposed between the gate and the semiconductor pattern. The source and the drain are separated from each other and disposed corresponding to the semiconductor pattern. At least one of the source and the drain has a first copper patterned layer and a first copper oxynitride patterned layer. The first copper oxynitride patterned layer covers the first copper patterned layer. The first copper patterned layer is disposed between the first copper oxynitride patterned layer and the first substrate. Moreover, a manufacturing method of the semiconductor device is also provided.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Applicant: Au Optronics Corporation
    Inventors: Ting-Fong Chien, Po-Liang Yeh, Chen-Chung Wu, Chia-Ming Chang, Chun-An Chang
  • Patent number: 10866286
    Abstract: A connection detection system and a connection detection method are provided. The connection detection system includes a connector, an expansion dock and a signal transmitter. The connector has a first detecting pin and a second detecting pin. The second detecting pin receives a first signal or a second signal from the first detecting pin when the expansion dock is connected to the connector. The signal transmitter is coupled to the connector. The signal transmitter is configured to receive a detection signal through the second detecting pin and determine whether the connector is connected to the expansion dock according to the sensing signal. The signal transmitter provides the first signal to the first detecting pin when the connector is not connected to the expansion dock. The signal transmitter provides the second signal to the second detecting pin when the connector is connected to the expansion dock.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 15, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Yi-Tso Chang, Po-Liang Yeh
  • Publication number: 20200303553
    Abstract: A semiconductor structure disposed on a substrate including a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopping pattern disposed on the oxide semiconductor layer, and a second metal layer disposed on the etch stopping layer. The first metal layer includes a gate line. The gate insulating layer covers the gate line. Patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern. The etch stopping layer is located between the second metal layer and the oxide semiconductor layer. The second metal layer includes a signal line disposed on the etch stopping layer and is electrically connected to the oxide semiconductor pattern. A manufacturing method of the semiconductor structure is also provided.
    Type: Application
    Filed: July 4, 2019
    Publication date: September 24, 2020
    Applicant: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, De-Zhang Deng, Chia-Ming Chang
  • Publication number: 20190341494
    Abstract: A semiconductor device including a first substrate and a thin film transistor disposed on the first substrate is provided. The thin film transistor includes a gate, a semiconductor pattern, a first insulating layer, a source and a drain. The first insulating layer is disposed between the gate and the semiconductor pattern. The source and the drain are separated from each other and disposed corresponding to the semiconductor pattern. At least one of the source and the drain has a first copper patterned layer and a first copper oxynitride patterned layer. The first copper oxynitride patterned layer covers the first copper patterned layer. The first copper patterned layer is disposed between the first copper oxynitride patterned layer and the first substrate. Moreover, a manufacturing method of the semiconductor device is also provided.
    Type: Application
    Filed: November 1, 2018
    Publication date: November 7, 2019
    Applicant: Au Optronics Corporation
    Inventors: Ting-Fong Chien, Po-Liang Yeh, Chen-Chung Wu, Chia-Ming Chang, Chun-An Chang
  • Publication number: 20190277901
    Abstract: A connection detection system and a connection detection method are provided. The connection detection system includes a connector, an expansion dock and a signal transmitter. The connector has a first detecting pin and a second detecting pin. The second detecting pin receives a first signal or a second signal from the first detecting pin when the expansion dock is connected to the connector. The signal transmitter is coupled to the connector. The signal transmitter is configured to receive a detection signal through the second detecting pin and determine whether the connector is connected to the expansion dock according to the sensing signal. The signal transmitter provides the first signal to the first detecting pin when the connector is not connected to the expansion dock. The signal transmitter provides the second signal to the second detecting pin when the connector is connected to the expansion dock.
    Type: Application
    Filed: December 12, 2018
    Publication date: September 12, 2019
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Tso Chang, Po-Liang Yeh
  • Patent number: 9905701
    Abstract: An active device structure and a method of fabricating an active device are provided. The active device structure includes a gate, an oxide channel layer, a source, a drain and a high power deposited insulation layer. The gate and the oxide channel layer are overlapped in a top and bottom manner. The oxide channel layer includes a top layer and a bottom layer having a crystalline structure different from a crystalline structure of the top layer. The source and the drain both contact the oxide channel layer, wherein a gap separating the source and the drain defines a channel area. The high power deposited insulation layer contacts the top layer of the oxide channel layer. The top layer of the oxide channel layer provides the effect of blocking light, which solves the problem of threshold voltage shift due to the light irradiation on the oxide channel layer.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: February 27, 2018
    Assignee: Au Optronics Corporation
    Inventors: Po-Liang Yeh, Chen-Chung Wu, Chun-An Chang, Jiang-Jin You, Chia-Ming Chang
  • Publication number: 20160300951
    Abstract: An active device structure and a method of fabricating an active device are provided. The active device structure includes a gate, an oxide channel layer, a source, a drain and a high power deposited insulation layer. The gate and the oxide channel layer are overlapped in a top and bottom manner. The oxide channel layer includes a top layer and a bottom layer having a crystalline structure different from a crystalline structure of the top layer. The source and the drain both contact the oxide channel layer, wherein a gap separating the source and the drain defines a channel area. The high power deposited insulation layer contacts the top layer of the oxide channel layer. The top layer of the oxide channel layer provides the effect of blocking light, which solves the problem of threshold voltage shift due to the light irradiation on the oxide channel layer.
    Type: Application
    Filed: March 16, 2016
    Publication date: October 13, 2016
    Inventors: Po-Liang Yeh, Chen-Chung Wu, Chun-An Chang, Jiang-Jin You, Chia-Ming Chang
  • Patent number: 8704220
    Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 22, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng
  • Patent number: 8698150
    Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: April 15, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
  • Publication number: 20130328069
    Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.
    Type: Application
    Filed: October 4, 2012
    Publication date: December 12, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
  • Publication number: 20130119371
    Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.
    Type: Application
    Filed: April 12, 2012
    Publication date: May 16, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng