Patents by Inventor Po-Lin PENG

Po-Lin PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961834
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Patent number: 11929363
    Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Publication number: 20240079408
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • Patent number: 11908859
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Patent number: 11855088
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Publication number: 20230299576
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Patent number: 11710962
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.
    Type: Grant
    Filed: May 29, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Publication number: 20220310589
    Abstract: An IC device includes a first power terminal, an IO pad, a first ESD protection device coupled between the first power terminal and IO pad, a first trigger current source device coupled between the first power terminal and IO pad, and a semiconductor substrate over which the first ESD protection device and first trigger current source device are formed. The first ESD protection device includes a parasitic BJT having a collector and an emitter coupled between the IO pad and first power terminal, and a base coupled via a substrate resistance to a well tap coupled to the first power terminal. The first trigger current source device, in response to an ESD voltage on the IO pad, becomes conductive and causes discharge of the ESD voltage through the first ESD protection device to the first power terminal.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Po-Lin PENG, Yu-Ti SU
  • Publication number: 20220294212
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.
    Type: Application
    Filed: May 29, 2022
    Publication date: September 15, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Publication number: 20220223582
    Abstract: An integrated circuit includes a diode string, a first transistor, a second transistor, and a third transistor. The diode string is coupled between a first reference voltage pin and an input/output (I/O) pad. A first terminal of the second transistor is coupled to a first node, and a gate terminal of the second transistor is coupled to a second reference voltage pin. In response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to a gate terminal of the first transistor.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 14, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU
  • Publication number: 20220208753
    Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Publication number: 20220208752
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Patent number: 11355927
    Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Publication number: 20220130824
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • Publication number: 20220130825
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • Patent number: 11289472
    Abstract: An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su
  • Patent number: 11282831
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Publication number: 20220037310
    Abstract: An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU
  • Publication number: 20220029414
    Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Patent number: 11222893
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee