Abstract: A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.

Abstract: Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.

Abstract: A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.

Abstract: Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.