Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.

Abstract: The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.

Abstract: Variable gain amplifiers with controllable gain gradient over temperature. A variable gain amplification circuit comprises an input terminal receiving an input signal, an output terminal outputting an output signal, and a control terminal receiving a first gain control signal. The relationship between gain of the variable gain amplification circuit and temperature is programmable rather than temperature independent, and is controlled by the first gain control signal obtained by a second gain control signal and a third gain control signal.

Abstract: Linear-in-dB current generators having a maximum gain with least gain error. A first transistor is coupled between a first node and a first power voltage, and a first resistor is coupled between the first transistor and a second node. A second transistor is coupled between the second node and a second power voltage and comprises a control terminal coupled to the first node, and a third transistor comprises a first terminal coupled to the second power voltage, and a control terminal coupled to the first node. A second resistor is coupled between the third transistor and a third node, and a fourth transistor comprises a first terminal coupled to the first terminal, and a control terminal coupled to the third node. A first current source and the second current source are coupled to the second node and the third node respectively, and a reference current source is coupled to the first node.

Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.

Abstract: Linear-in-dB current generators having a maximum gain with least gain error. A first transistor is coupled between a first node and a first power voltage, and a first resistor is coupled between the first transistor and a second node. A second transistor is coupled between the second node and a second power voltage and comprises a control terminal coupled to the first node, and a third transistor comprises a first terminal coupled to the second power voltage, and a control terminal coupled to the first node. A second resistor is coupled between the third transistor and a third node, and a fourth transistor comprises a first terminal coupled to the first terminal, and a control terminal coupled to the third node. A first current source and the second current source are coupled to the second node and the third node respectively, and a reference current source is coupled to the first node.

Abstract: The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.