Patents by Inventor Po Shao LIN

Po Shao LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901410
    Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Po-Shao Lin, Wei-Yang Lee
  • Publication number: 20230282723
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure formed over a substrate, and the first fin structure includes a plurality of first nanostructures stacked in a vertical direction. The semiconductor device structure further includes a second fin structure formed over the substrate, and the second fin structure includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure further includes a dummy fin structure between the first fin structure and the second fin structure. The dummy fin structure includes a first etching stop layer between a bottom portion and a top portion.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Shao LIN, Yi-Hsiu LIU, Chih-Chung CHANG, Chung-Ting KO, Sung-En LIN
  • Publication number: 20230063463
    Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yen-Ting Chen, Po-Shao Lin, Wei-Yang Lee
  • Publication number: 20230062597
    Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Kai LIN, Shih-Chiang CHEN, Po-Shao LIN, Wei-Yang LEE, Chia-Pin LIN, Yuan-Ching PENG
  • Publication number: 20230018266
    Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.
    Type: Application
    Filed: May 5, 2022
    Publication date: January 19, 2023
    Inventors: Wei-Han Fan, Chia-Pin Lin, Wei-Yang Lee, Tzu-Hua Chiu, Kuan-Hao Cheng, Po Shao Lin
  • Publication number: 20230017036
    Abstract: A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.
    Type: Application
    Filed: May 4, 2022
    Publication date: January 19, 2023
    Inventors: Wei-Han FAN, Chia-Pin LIN, Wei-Yang LEE, Tzu-Hua CHIU, Kuan-Hao CHENG, Po Shao LIN