Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: A gate driver circuit is provided. The gate driver circuit includes a plurality of gate driver units. The gate driver units are coupled to each other in sequence, and each of the gate driver units includes a shift register and a de-multiplexer. The shift register receives one of a plurality of operation clock signals and a startup signal and generates a first control signal and a second control signal according to the startup signal and the received operation clock signal. The de-multiplexer is coupled to the shift register and receives a portion of a plurality of gate clock signals to output the received portion of the gate clock signals according to the first control signal to generate a plurality of gate signals in sequence. The gate clock signals are enabled in sequence, and enabling durations of two consecutive clock signals in the gate clock signals are partially overlapped.