Patents by Inventor Po-Sheng LU
Po-Sheng LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112842Abstract: An inductor and a method of forming the same are provided. The inductor includes a patterned wire structure. The patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. The conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. The dielectric film covers the outer surface. The magnetic shell covers the dielectric film. The dielectric film is between the conductive core and the magnetic shell.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Lu, Chien-Hung Liu, Nuo Xu
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Publication number: 20240016066Abstract: A memory device includes a substrate, a reference layer, a tunneling layer, a film stack, and a capping layer. The reference layer is disposed on the substrate. The tunneling layer is disposed on the reference layer. The film stack is formed over the tunneling layer and on the substrate, wherein the film stack includes a first free layer, a spacer with high exchange stiffness constant and a second free layer. The first free layer is in contact with the tunneling layer and the film stack. The spacer with high exchange stiffness constant is sandwiched between the first free layer and the second free layer. The capping layer is disposed on and electrically connected to the film stack.Type: ApplicationFiled: July 10, 2022Publication date: January 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Lu, Zhi-Ren Xiao, Nuo Xu, Zhiqiang Wu
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Publication number: 20230389447Abstract: A method of forming a semiconductor device includes providing a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Tsung-Chieh Hsiao, Po-Sheng Lu, Wei-Chih Wen, Liang-Wei Wang, Yu-Jen Wang, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20230354718Abstract: A magnetic tunnel junction (MTJ) stack includes a reference layer, a tunnel barrier layer, a free layer, and a superparamagnetic layer. The reference layer has a fixed magnetization direction. The tunnel barrier layer is disposed on the reference layer, and includes an insulating material. The free layer has a changeable magnetization direction, and is disposed on the tunnel barrier layer opposite to the reference layer. The superparamagnetic layer is disposed on the free layer opposite to the tunnel barrier layer. Methods for manufacturing the MTJ stack are also disclosed.Type: ApplicationFiled: May 2, 2022Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nuo XU, Po-Sheng LU, Zhi-Ren XIAO, Zhiqiang WU
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Publication number: 20230221645Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate While spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: ApplicationFiled: February 27, 2023Publication date: July 13, 2023Inventors: Ming-Hsuan CHUANG, Po-Sheng LU, Shou-Wen KUO, Cheng-Yi HUANG, Chia-Hung CHU
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Publication number: 20230197633Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.Type: ApplicationFiled: February 23, 2023Publication date: June 22, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nuo Xu, Yuan-Hao Chang, Po-Sheng Lu, Zhiqiang Wu
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Publication number: 20230123764Abstract: An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.Type: ApplicationFiled: February 2, 2022Publication date: April 20, 2023Inventors: Nuo Xu, Yuan Hao Chang, Po-Sheng Lu, Zhiqiang Wu
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Patent number: 11610848Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.Type: GrantFiled: June 7, 2021Date of Patent: March 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nuo Xu, Yuan-Hao Chang, Po-Sheng Lu, Zhiqiang Wu
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Patent number: 11592748Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: GrantFiled: November 14, 2019Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsuan Chuang, Po-Sheng Lu, Shou-Wen Kuo, Cheng-Yi Huang, Chia-Hung Chu
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Publication number: 20220392847Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nuo Xu, Yuan-Hao Chang, Po-Sheng Lu, Zhiqiang Wu
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Publication number: 20220359819Abstract: A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.Type: ApplicationFiled: November 11, 2021Publication date: November 10, 2022Inventors: Chih-Fan Huang, Po-Sheng Lu, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220328561Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.Type: ApplicationFiled: August 20, 2021Publication date: October 13, 2022Inventors: Jui-Lin CHEN, Chenchen Jacob WANG, Hsin-Wen SU, Ping-Wei WANG, Yuan-Hao CHANG, Po-Sheng LU, Shih-Hao LIN
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Publication number: 20220140228Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.Type: ApplicationFiled: March 19, 2021Publication date: May 5, 2022Inventors: Tsung-Chieh Hsiao, Po-Sheng Lu, Wei-Chih Wen, Liang-Wei Wang, Yu-Jen Wang, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11145521Abstract: A method for cleaning a semiconductor substrate is provided. The method includes the steps of: applying a first agent onto a top surface of the semiconductor substrate while the semiconductor substrate is rotated at a first rotational frequency; immersing the semiconductor substrate in a second agent while rotating the semiconductor substrate at a second rotational frequency; and rotating the semiconductor substrate at a third rotational frequency while a third agent is introduced onto the top surface of the semiconductor substrate. The first rotational frequency may be greater than the third rotational frequency and the third rotational frequency is greater than the second rotational frequency. In some embodiments, the second rotational frequency is zero and the semiconductor substrate is held stationary during the immersing step.Type: GrantFiled: September 28, 2017Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mei Hui Tsai, Hsiao-Yi Wang, Yen-Min Liao, Po-Sheng Lu
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Publication number: 20200192225Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: ApplicationFiled: November 14, 2019Publication date: June 18, 2020Inventors: Ming-Hsuan CHUANG, Po-Sheng LU, Shou-Wen KUO, Cheng-Yi HUANG, Chia-Hung CHU
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Publication number: 20190096707Abstract: A method for cleaning a semiconductor substrate is provided. The method includes the steps of: applying a first agent onto a top surface of the semiconductor substrate while the semiconductor substrate is rotated at a first rotational frequency; immersing the semiconductor substrate in a second agent while rotating the semiconductor substrate at a second rotational frequency; and rotating the semiconductor substrate at a third rotational frequency while a third agent is introduced onto the top surface of the semiconductor substrate. The first rotational frequency may be greater than the third rotational frequency and the third rotational frequency is greater than the second rotational frequency. In some embodiments, the second rotational frequency is zero and the semiconductor substrate is held stationary during the immersing step.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mei Hui TSAI, Hsiao-Yi WANG, Yen-Min LIAO, Po-Sheng LU