Abstract: A pixel data preprocessing method includes the steps of: inputting a first frame data into a timing controller; performing a differential operation on the first frame data to generate a first frame differential data; writing the first frame differential data into a frame memory with the timing controller; reading a second frame differential data from the frame memory with the timing controller; performing an inverse differential operation on the second frame differential data to generate a second frame data; comparing the first frame data and the second frame data; and outputting a driving data with the timing controller according to a comparison result of comparing the first frame data and the second frame data. The present invention further provides a pixel data preprocessing circuit.

Abstract: A pixel structure includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first switching transistor and a first liquid crystal capacitor, wherein when the first switching transistor is turned on, the first liquid crystal capacitor is biased to a first gray level voltage. The second sub-pixel includes a second switching transistor, a second liquid crystal capacitor, a third switching transistor, a charge sharing capacitor and a fourth switching transistor, wherein when the second switching transistor is turned on, the second liquid crystal capacitor is biased to the first gray level voltage; when the fourth switching transistor is turned on, the charge sharing capacitor is reset to a predetermined voltage; and when the third switching transistor is turned on, the second liquid crystal capacitor and the charge sharing capacitor are charge-shared to a second gray level voltage through the third switching transistor.

Abstract: A pixel data preprocessing method includes the steps of: inputting a first frame data into a timing controller; performing a differential operation on the first frame data to generate a first frame differential data; writing the first frame differential data into a frame memory with the timing controller; reading a second frame differential data from the frame memory with the timing controller; performing an inverse differential operation on the second frame differential data to generate a second frame data; comparing the first frame data and the second frame data; and outputting a driving data with the timing controller according to a comparison result of comparing the first frame data and the second frame data. The present invention further provides a pixel data preprocessing circuit.

Abstract: A pixel structure includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first switching transistor and a first liquid crystal capacitor, wherein when the first switching transistor is turned on, the first liquid crystal capacitor is biased to a first gray level voltage. The second sub-pixel includes a second switching transistor, a second liquid crystal capacitor, a third switching transistor, a charge sharing capacitor and a fourth switching transistor, wherein when the second switching transistor is turned on, the second liquid crystal capacitor is biased to the first gray level voltage; when the fourth switching transistor is turned on, the charge sharing capacitor is reset to a predetermined voltage; and when the third switching transistor is turned on, the second liquid crystal capacitor and the charge sharing capacitor are charge-shared to a second gray level voltage through the third switching transistor.