Patents by Inventor Po SHI
Po SHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002768Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.Type: GrantFiled: August 27, 2021Date of Patent: June 4, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Publication number: 20230378980Abstract: Embodiments of this application disclose a communication circuit, including: a shared radio frequency circuit, a baseband processing circuit, and an antenna. The antenna is configured to receive and send a first-mode signal and a second-mode signal. The shared radio frequency circuit is coupled between the baseband processing circuit and the antenna, and the shared radio frequency circuit is configured to process the first-mode signal and the second-mode signal in a time-division manner. The shared radio frequency circuit includes a slave control interface, and the baseband processing circuit includes a master control interface. The master control interface is coupled to the slave control interface by using a control bus, and is used for configuring the shared radio frequency circuit to process the first-mode signal and the second-mode signal in the time-division manner.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Weinan Li, Weitao Jing, Po Shi
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Publication number: 20230188104Abstract: Example power amplifier chips and communication devices are described. One example power amplifier chip includes a package housing and a plurality of power amplifier dies. The plurality of power amplifier dies are packaged in the package housing, and each of the plurality of power amplifier dies includes at least one stage of power amplifier.Type: ApplicationFiled: February 15, 2023Publication date: June 15, 2023Inventors: Wei XU, Po SHI, Zhengde YANG, Yufeng WANG, Junhao ZOU, Qingquan LUO, Shengchang SHANGGUAN
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Patent number: 9891273Abstract: Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.Type: GrantFiled: June 29, 2011Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Hsin Kuo, Wensen Hung, Po-Shi Yao
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Patent number: 9417263Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.Type: GrantFiled: August 8, 2014Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Hsin Kuo, Wensen Hung, Po-Shi Yao
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Publication number: 20140347085Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Inventors: Yung-Hsin KUO, Wensen HUNG, Po-Shi YAO
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Patent number: 8832933Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.Type: GrantFiled: September 15, 2011Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Hsin Kuo, Wensen Hung, Po-Shi Yao
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Publication number: 20130069683Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process.Type: ApplicationFiled: September 15, 2011Publication date: March 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Hsin KUO, Wensen HUNG, Po-Shi YAO
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Publication number: 20130002282Abstract: Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Hsin Kuo, Wensen Hung, Po-Shi Yao