Patents by Inventor Po-Tsang Huang
Po-Tsang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411388Abstract: An IC structure includes a first transistor, a dielectric layer, a plurality of semiconductor pillars, a plurality of semiconductor plugs, a semiconductor structure, and a second transistor. The first transistor is formed on a substrate. The dielectric layer is above the first transistor. The semiconductor pillars extend from the substrate into the dielectric layer. The semiconductor plugs extend from a top surface of the dielectric layer into the dielectric layer to the plurality of semiconductor pillars. The semiconductor structure is disposed over the top surface of the dielectric layer. The second transistor is formed on the semiconductor structure.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung UniversityInventors: Chenming HU, Kuan-Neng CHEN, Po-Tsang HUANG, Hao-Tung CHUNG, Bo-Jheng SHIH, Yu-Ming PAN
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Publication number: 20220367445Abstract: A method includes following steps. An interconnect structure is formed over a first transistor. A dielectric layer is formed over the interconnect structure. The dielectric layer is etched to form holes in the dielectric layer. An amorphous layer is deposited in the holes of the dielectric layer and on a top surface of the dielectric layer. The amorphous layer is crystallized into a polycrystalline layer. A second transistor is formed on the polycrystalline layer.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Po-Tsang HUANG
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Patent number: 11457850Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.Type: GrantFiled: December 5, 2019Date of Patent: October 4, 2022Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Hung-Pin Lu, Po-Tsang Huang, Wei Hwang
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Publication number: 20200178823Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.Type: ApplicationFiled: December 5, 2019Publication date: June 11, 2020Inventors: Hung-Pin LU, Po-Tsang HUANG, Wei HWANG
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Patent number: 9395768Abstract: A flash drive including a housing, a storage module, and at least one elastic member is provided. The housing is flexible and an inner space is formed by the housing. The storage module is movably disposed in the inner space. The elastic member is disposed in the inner space and connected between the storage module and the housing. The housing is adapted to be deformed by a force to compress the inner space, so as to drive a portion of the storage module to be exposed outside the housing and deform the elastic member.Type: GrantFiled: September 22, 2014Date of Patent: July 19, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Po-Tsang Huang, Chun-Yao Chang
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Publication number: 20160054766Abstract: A flash drive including a housing, a storage module, and at least one elastic member is provided. The housing is flexible and an inner space is formed by the housing. The storage module is movably disposed in the inner space. The elastic member is disposed in the inner space and connected between the storage module and the housing. The housing is adapted to be deformed by a force to compress the inner space, so as to drive a portion of the storage module to be exposed outside the housing and deform the elastic member.Type: ApplicationFiled: September 22, 2014Publication date: February 25, 2016Inventors: Po-Tsang Huang, Chun-Yao Chang
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Patent number: 8773894Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.Type: GrantFiled: November 26, 2012Date of Patent: July 8, 2014Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Chien-Yu Lu, Chien-Hen Chen, Chi-Shin Chang, Po-Tsang Huang, Shu-Lin Lai, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu
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Publication number: 20140078818Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.Type: ApplicationFiled: November 26, 2012Publication date: March 20, 2014Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Ching-Te CHUANG, Hao-I YANG, Chien-Yu LU, Chien-Hen CHEN, Chi-Shin CHANG, Po-Tsang HUANG, Shu-Lin LAI, Wei HWANG, Shyh-Jye JOU, Ming-Hsien TU
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Patent number: 8427224Abstract: On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.Type: GrantFiled: July 26, 2011Date of Patent: April 23, 2013Assignee: National Chiao Tung UniversityInventors: Tien-Hung Lin, Po-Tsang Huang, Wei Hwang
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Publication number: 20130028324Abstract: A method and device for decoding a scalable video signal utilizing an inter-layer prediction are provided herein. An inter-layer pre-fetch scheme (IPS) is presented to improve the performance for scalable video coding (SVC) decoder. With proposed invention, the required information for inter-layer prediction in SVC technique will be pre-fetched ahead when reconstructing the enhancement layer so that the cache miss rate can be reduced significantly. Accordingly, the execution time and memory energy consumptions can be improved.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: YUNG CHANG, PO-TSANG HUANG, WEI HWANG, YU-CHEN CHEN, GWO-LONG LI, TIAN-SHEUAN CHANG
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Publication number: 20130027122Abstract: On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.Type: ApplicationFiled: July 26, 2011Publication date: January 31, 2013Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: TIEN-HUNG LIN, PO-TSANG HUANG, WEI HWANG
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Publication number: 20130031327Abstract: Different processor elements in multi-task/multi-core system on chip may have different memory requirements at runtime. The method for adaptively allocating cache memory re-allocates the cache resource by updating the bank assignment table. According to the associativity-based partitioning scheme, centralized memory is separated into several groups of SRAM banks which are numbered differently. These groups are assigned to different processor elements to be L2 caches. The bank assignment information is recoded in bank assignment table, and is updated by system profiling engine. By changing the information in bank assignment table, the cache resource re-allocation for processor elements is achieved.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: Yung CHANG, Po-Tsang Huang, Wei Hwang
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Patent number: 8072818Abstract: The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.Type: GrantFiled: December 30, 2009Date of Patent: December 6, 2011Assignee: National Chiao Tung UniversityInventors: Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
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Patent number: 7903443Abstract: The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.Type: GrantFiled: February 15, 2007Date of Patent: March 8, 2011Assignee: National Chiao Tung UniversityInventors: Po-Tsang Huang, Wei Hwang, Shu-Wei Chang
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Publication number: 20100172194Abstract: The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.Type: ApplicationFiled: December 30, 2009Publication date: July 8, 2010Applicant: National Chiao Tung UniversityInventors: Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
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Patent number: 7738275Abstract: A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.Type: GrantFiled: January 16, 2008Date of Patent: June 15, 2010Assignee: National Chiao Tung UniversityInventors: Po-Tsang Huang, Wen-Yen Liu, Wei Hwang
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Patent number: 7616469Abstract: A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells.Type: GrantFiled: January 16, 2008Date of Patent: November 10, 2009Assignee: National Chiao Tung UniversityInventors: Po-Tsang Huang, Wen-Yen Liu, Wei Hwang
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Publication number: 20090161400Abstract: A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.Type: ApplicationFiled: January 16, 2008Publication date: June 25, 2009Inventors: Po-Tsang Huang, Wen-Yen Liu, Wei Hwang
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Patent number: D757397Type: GrantFiled: March 16, 2015Date of Patent: May 31, 2016Assignee: Well & David Corp.Inventor: Po-Tsang Huang
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Patent number: D777551Type: GrantFiled: October 1, 2014Date of Patent: January 31, 2017Inventor: Po-Tsang Huang