Patents by Inventor Po Wang

Po Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140765
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a plurality of photonic integrated circuit chips and an auxiliary electronic element are separately configured on a package module to shorten the transmission distance of the optical signal. Therefore, the signal transmission rate of a circuit structure can be increased, thereby improving the overall operating performance of the electronic package.
    Type: Application
    Filed: April 10, 2024
    Publication date: May 1, 2025
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG
  • Publication number: 20250132221
    Abstract: An electronic package is provided and includes: a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure disposed on the electronic component, a heat conductor sandwiched between the electronic component and the heat dissipation structure, a first intermetallic compound layer formed between the heat dissipation structure and the heat conductor, and a second intermetallic compound layer formed between the heat conductor and the electronic component. Therefore, stable connections can be formed between the heat dissipation structure, the heat conductor and the electronic component via the first intermetallic compound layer and the second intermetallic compound layer to improve heat dissipation effect.
    Type: Application
    Filed: June 26, 2024
    Publication date: April 24, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Dai-Fei LI, Liang-Yi HUNG, Chia-Cheng CHEN, Yu-Po WANG
  • Publication number: 20250105068
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a first barrier body and a second barrier body are disposed respectively, and a heat dissipation structure is formed with a hole thereon. Thereby, gas in the heat dissipation structure can be discharged via the hole, so as to prevent the gas from remaining in a thermal conductive layer and affecting the heat dissipation effect.
    Type: Application
    Filed: July 2, 2024
    Publication date: March 27, 2025
    Inventors: Chuan-Shun LI, Pin-Jing SU, Liang-Yi HUNG, Chia-Cheng CHEN, Yu-Po WANG
  • Publication number: 20250102750
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a first optoelectronic element having a first optical fiber connection portion is disposed on an electronic module, a second optoelectronic element having a second optical fiber connection portion is disposed on a first level layer of a lower carrying portion of a step-shaped carrier structure, and the electronic module is disposed on a second level layer of the step-shaped carrier structure and the second optoelectronic element having the second optical fiber connection portion, so that the electronic module is electrically connected to the second optoelectronic element having the second optical fiber connection portion. Thereby, two optoelectronic elements having optical fiber connection portions can be easily and vertically integrated, and the second optoelectronic element can be stably carried by the step-shaped carrier structure.
    Type: Application
    Filed: February 2, 2024
    Publication date: March 27, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shuai-Lin LIU, Nai-Hao KAO, Yu-Po WANG
  • Publication number: 20250098156
    Abstract: A method for forming a semiconductor structure includes the following steps. A first trench is formed in a semiconductor substrate, and a first nitride layer is formed along a sidewall and a bottom surface of the first trench. A first oxide layer is formed over the first nitride layer to fill the first trench, and the first oxide layer is recessed from the first trench to form a first recess. A portion of the first nitride layer exposed from the first recess is etched, and a second nitride layer is formed along a sidewall and a bottom surface of the first recess. The second nitride layer includes a first portion along the bottom surface and a second portion along the sidewall. The second portion is removed, and a second oxide layer is formed over the first portion to fill the first recess.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Inventors: Wei-Che CHANG, Kai JEN, Yu-Po WANG
  • Publication number: 20250087601
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Po-Yuan SU
  • Patent number: 12218513
    Abstract: A power transfer device including an AC power source unit and a single power transfer element, and a power reception device including a single power reception element electrically coupled to the power transfer element and a power reception circuit outputting power are included. The power reception circuit includes a different potential field disposed at a position that is an electric field formed by the power transfer element and at which intensity of the electric field is different from intensity of an electric field formed at a position of the power reception element.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: February 4, 2025
    Assignee: THE UNIVERSITY OF TOKYO
    Inventors: Shinichi Warisawa, Yen Po Wang, Munemasa Sugimoto
  • Publication number: 20250038113
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Shuai-Lin LIU
  • Patent number: 12199047
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 14, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Patent number: 12193221
    Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: January 7, 2025
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Wei-Che Chang, Kai Jen, Yu-Po Wang
  • Patent number: 12176291
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 24, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
  • Patent number: 12142451
    Abstract: A system for grounding a mask using a grounding component are provided. Some embodiments of the system include a grounding component comprising a base and an extension protruding from the base and comprising a conductive prong configured to contact a conductive layer of the mask. Some embodiments of the system include a plurality of conductive prongs configured to contact multiple positions of a conductive layer of the mask. Some other embodiments of the system include an extension comprising various shapes.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 12, 2024
    Assignee: ASML Netherlands B.V.
    Inventors: Tianming Chen, Chiyan Kuan, Yixiang Wang, Zhi Po Wang
  • Publication number: 20240371721
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 7, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG
  • Publication number: 20240363577
    Abstract: An electronic package and a substrate structure thereof are provided, in which an electronic element and a flow stopper surrounding the electronic element are disposed on a substrate body of the substrate structure, and a heat dissipation structure is bonded on the electronic element via a heat dissipation material, so that the flow stopper limits an overflow range of the heat dissipation material to prevent the heat dissipation material from contaminating a circuit layer on the substrate body.
    Type: Application
    Filed: July 24, 2023
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pin-Jing SU, Wen-Yu TENG, Liang-Yi HUNG, Chia-Cheng CHEN, Yu-Po WANG
  • Publication number: 20240355578
    Abstract: Disclosed are non-transitory computer-readable media, systems, and computer-implemented methods that describe obtaining hot spot (HS) location information with respect to a printed pattern; obtaining LFP search criteria for searching the printed pattern to determine a local focus point (LFP) for an imaging device; selecting a HS area in the printed pattern that contains a HS; and determining the LFP proximate to the HS area based on the LFP search criteria, the LFP not containing the HS.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Te-Sheng WANG, Szu-Po WANG, Kai-Yuan CHI
  • Patent number: 12118465
    Abstract: A method includes steps of: based on training sets of gastrointestinal images, using a predetermined machine learning algorithm to obtain a preliminary model; feeding preliminary validation sets of gastrointestinal images into the preliminary model to obtain estimation results; based on the estimation results, selecting, from the preliminary validation sets of gastrointestinal images, a series of successive images as a selected validation set of gastrointestinal images; based on the selected validation set of gastrointestinal images, tuning parameters of the preliminary model to result in a speed-determining model for determining a moving speed of an endoscope camera.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 15, 2024
    Assignee: MIRLE AUTOMATION CORPORATION
    Inventors: Ching-Liang Lu, Yen-Po Wang, Yuan-Chia Chu, Ying-Chun Jheng, Li-Sung Fan Chiang, Tsung-Chieh Liu
  • Publication number: 20240321672
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic structure and a wall structure surrounding the electronic structure are disposed on a carrier structure, a heat conducting layer is formed on the electronic structure, and the wall structure and the heat conducting layer are covered by a heat dissipation element. Therefore, a thermal stress can be effectively dispersed by the arrangement of the wall structure, such that a warpage of the electronic structure and a heat dissipation body can be effectively controlled.
    Type: Application
    Filed: July 12, 2023
    Publication date: September 26, 2024
    Inventors: Cheng-Lun CHEN, Liang-Yi HUNG, Yu-Po WANG
  • Publication number: 20240321628
    Abstract: A method for forming semiconductor structures is provided. The method includes forming a first patterning photoresist layer having a first opening on a first patterning layer, trimming the first patterning photoresist layer, transferring the first pattern of the trimmed first patterning photoresist layer to the first patterning layer, performing a first pattern reversal process to reverse the first pattern of the first patterning layer into the second opening, forming a second patterning layer in and on the second opening, forming a second patterning photoresist layer having a third opening on the second patterning layer, transferring the second pattern of the second patterning photoresist layer to a first stacking layer, performing a second pattern reversal process to reverse a third pattern between the second opening and the third opening into a fourth opening, and extending the fourth opening to the substrate.
    Type: Application
    Filed: September 28, 2023
    Publication date: September 26, 2024
    Inventors: Yu-Po WANG, Te-Hsuan PENG
  • Publication number: 20240290701
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 29, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Patent number: 12068545
    Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: August 20, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu