Abstract: A data storage device includes a memory device and a memory controller. The memory device has a corresponding total storage capacity and includes multiple memory blocks. The total storage capacity is set to a maximum storage capacity provided by the memory blocks by default. The memory blocks include one or more predetermined memory blocks configured as a buffer to receive data from a host device. The memory controller is coupled to the memory device to access the memory device. In response to setting of a maximum amount of write data, the memory controller determines a value of the total storage capacity according to the maximum amount of write data, and determines a number of said one or more predetermined memory blocks according to the value of the total storage capacity and the maximum storage capacity.

Abstract: A memory controller includes an error correction code engine, a buffer memory and a microprocessor. In response to a first decoding result of predetermined data, the microprocessor performs a repeated read operation on a memory device to obtain multiple read results of a data chunk having the predetermined data. The data chunk includes multiple bits. The microprocessor further performs a data reconstruction and error correction procedure according to the read results of the data chunk. In an operation of data reconstruction, the microprocessor determines a bit value corresponding to each bit in the data chunk according to the read results of the data chunk to generate a reconstructed data chunk. In an operation of error correction, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the predetermined data.

Abstract: A data storage device includes a memory device and a memory controller. The memory device has a corresponding total storage capacity and includes multiple memory blocks. The total storage capacity is set to a maximum storage capacity provided by the memory blocks by default. The memory blocks include one or more predetermined memory blocks configured as a buffer to receive data from a host device. The memory controller is coupled to the memory device to access the memory device. In response to setting of a maximum amount of write data, the memory controller determines a value of the total storage capacity according to the maximum amount of write data, and determines a number of said one or more predetermined memory blocks according to the value of the total storage capacity and the maximum storage capacity.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.

Abstract: A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.

Abstract: A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Abstract: A memory controller includes an error correction code engine, a buffer memory and a microprocessor. In response to a first decoding result of predetermined data, the microprocessor performs a repeated read operation on a memory device to obtain multiple read results of a data chunk having the predetermined data. The data chunk includes multiple bits. The microprocessor further performs a data reconstruction and error correction procedure according to the read results of the data chunk. In an operation of data reconstruction, the microprocessor determines a bit value corresponding to each bit in the data chunk according to the read results of the data chunk to generate a reconstructed data chunk. In an operation of error correction, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the predetermined data.

Abstract: A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing an enabling signal to an output device, where the flash controller and the output device are disposed on a printed circuit board (PCB) and intercoupled through wires in the PCB; reading an opcode of the reliable command corresponding to a flash module from the output device, where the flash module is disposed on the PCB and coupled to the flash controller through circuits in the PCB, and the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode; and stopping issuing the enabling signal to the output device after obtaining the opcode of the reliable command.

Abstract: A temperature detector is used to detect a temperature of a circuit under test, and includes a temperature coefficient component, a multiplier, an impedance component and a node. The temperature coefficient component is arranged in proximity to the circuit under test. A control terminal of the multiplier is coupled to a second terminal of the temperature coefficient component. The impedance component is coupled between the second terminal of the temperature coefficient component and the control terminal of the multiplier, or between a second terminal of the multiplier and a third voltage terminal. The node is formed between the second terminal of the temperature coefficient component and the control terminal of the multiplier. A voltage at the node and an amplified detection current flowing to a first terminal of the multiplier are positively correlated to the temperature of the circuit under test.

Abstract: An apparatus and a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.

Abstract: A temperature detector is used to detect a temperature of a circuit under test, and includes a temperature coefficient component, a multiplier, an impedance component and a node. The temperature coefficient component is arranged in proximity to the circuit under test. A control terminal of the multiplier is coupled to a second terminal of the temperature coefficient component. The impedance component is coupled between the second terminal of the temperature coefficient component and the control terminal of the multiplier, or between a second terminal of the multiplier and a third voltage terminal. The node is formed between the second terminal of the temperature coefficient component and the control terminal of the multiplier. A voltage at the node and an amplified detection current flowing to a first terminal of the multiplier are positively correlated to the temperature of the circuit under test.

Abstract: The invention relates to a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.

Abstract: A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory includes a first block and a second block, wherein the first block stores firmware code. The micro-controller writes one predetermined string into the second block before an execution of the firmware code, and determines whether there is more than one predetermined string in the second block. In response to there being no more than one predetermined string in the second block, the micro-controller allows the execution of the firmware code and erases the predetermined string in the second block upon successful completion of a prerequisite procedure during the execution of the firmware code. In response to there being more than one predetermined string in the second block, the micro-controller does not allow the execution of the firmware code.

Abstract: An access device includes a memory controller coupled to a memory device and configured to access the memory device. The memory controller is further configured to perform a test procedure on the memory device to obtain a test result, write a boot code index, which indicates a predetermined address for storing predetermined system data of the memory device and a copy rule adopted for generating one or more duplicates of the predetermined system data, in the memory device, establish system data of the memory device according to the test result, write the system data into the predetermined address as the predetermined system data, and write the system data in one or more memory blocks of the memory device as the duplicates of the predetermined system data according to the copy rule.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing an enabling signal to an output device, where the flash controller and the output device are disposed on a printed circuit board (PCB) and intercoupled through wires in the PCB; reading an opcode of the reliable command corresponding to a flash module from the output device, where the flash module is disposed on the PCB and coupled to the flash controller through circuits in the PCB, and the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode; and stopping issuing the enabling signal to the output device after obtaining the opcode of the reliable command.

Abstract: The invention introduces a non-transitory computer program product for activating a flash device when executed by a processing unit of the flash device to have program code to: determine whether the flash device is physically reset when the flash device enters a test mode perform an operation of a first phase for transmitting a very first message to a card-initialization host when the flash device is physically reset; and perform an operation of a second phase for searching a flash module for information referenced by In-System Programming (ISP) code, obtaining the ISP code from a designated address, and programming the ISP code into the flash module when the flash device is not physically reset.

Abstract: A method for performing page availability management of a memory device, the associated memory device and electronic device, and page availability management system are provided. The method may include: obtaining a set of page Error Correction Code (ECC) error tables of a non-volatile (NV) memory; based on a predetermined rule, finding respective local risky pages of at least one portion of blocks within a plurality of blocks according to the set of page ECC error tables, respectively, to generate local risky page counts respectively corresponding to page indexes; finding one or more global risky pages corresponding to one or more page indexes of the multiple page indexes according to the local risky page counts; and writing a global risky page table into the memory device, for controlling the memory device to skip using the one or more global risky pages of each of the plurality of blocks.

Abstract: A method for performing initialization in a memory device, the associated memory device and the controller thereof, and an associated electronic device are provided. The method may include: after a non-volatile (NV) memory within the memory device is powered on, searching for an empty-memory indicator in the NV memory, wherein the empty-memory indicator is applicable to determining whether the NV memory is empty; and according to whether the empty-memory indicator is found or not, selectively skipping or performing a program code search in the NV memory, to complete an initialization process, wherein the initialization process includes at least one initial setting of the memory device, and if the empty-memory indicator is found, the program code search is skipped, otherwise, the program code search is performed.