Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A fastener is adapted for assembling a first housing to a second housing. The first housing is provided with a protruding portion and a buckling portion, and the second housing has a first surface, a second surface, and a through hole. The fastener includes a first portion, at least one connecting portion, at least two elastic portions, and a second portion. The first portion movably abuts against the first surface and has a first opening. The connecting portion is accommodated in the through hole. One end of the connecting portion is connected to the first portion. The connecting portion is spaced apart from an inner edge of the second housing by a gap. The two elastic portions inclinedly extend into the first opening. The second portion movably abuts against the second surface and is disposed at the another end of the connecting portion.

Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.

Abstract: A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.

Abstract: A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Abstract: A memory controller includes an error correction code engine, a buffer memory and a microprocessor. In response to a first decoding result of predetermined data, the microprocessor performs a repeated read operation on a memory device to obtain multiple read results of a data chunk having the predetermined data. The data chunk includes multiple bits. The microprocessor further performs a data reconstruction and error correction procedure according to the read results of the data chunk. In an operation of data reconstruction, the microprocessor determines a bit value corresponding to each bit in the data chunk according to the read results of the data chunk to generate a reconstructed data chunk. In an operation of error correction, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the predetermined data.

Abstract: A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing an enabling signal to an output device, where the flash controller and the output device are disposed on a printed circuit board (PCB) and intercoupled through wires in the PCB; reading an opcode of the reliable command corresponding to a flash module from the output device, where the flash module is disposed on the PCB and coupled to the flash controller through circuits in the PCB, and the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode; and stopping issuing the enabling signal to the output device after obtaining the opcode of the reliable command.

Abstract: An apparatus and a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.

Abstract: A temperature detector is used to detect a temperature of a circuit under test, and includes a temperature coefficient component, a multiplier, an impedance component and a node. The temperature coefficient component is arranged in proximity to the circuit under test. A control terminal of the multiplier is coupled to a second terminal of the temperature coefficient component. The impedance component is coupled between the second terminal of the temperature coefficient component and the control terminal of the multiplier, or between a second terminal of the multiplier and a third voltage terminal. The node is formed between the second terminal of the temperature coefficient component and the control terminal of the multiplier. A voltage at the node and an amplified detection current flowing to a first terminal of the multiplier are positively correlated to the temperature of the circuit under test.

Abstract: A temperature detector is used to detect a temperature of a circuit under test, and includes a temperature coefficient component, a multiplier, an impedance component and a node. The temperature coefficient component is arranged in proximity to the circuit under test. A control terminal of the multiplier is coupled to a second terminal of the temperature coefficient component. The impedance component is coupled between the second terminal of the temperature coefficient component and the control terminal of the multiplier, or between a second terminal of the multiplier and a third voltage terminal. The node is formed between the second terminal of the temperature coefficient component and the control terminal of the multiplier. A voltage at the node and an amplified detection current flowing to a first terminal of the multiplier are positively correlated to the temperature of the circuit under test.

Abstract: The invention relates to a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.

Abstract: A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory includes a first block and a second block, wherein the first block stores firmware code. The micro-controller writes one predetermined string into the second block before an execution of the firmware code, and determines whether there is more than one predetermined string in the second block. In response to there being no more than one predetermined string in the second block, the micro-controller allows the execution of the firmware code and erases the predetermined string in the second block upon successful completion of a prerequisite procedure during the execution of the firmware code. In response to there being more than one predetermined string in the second block, the micro-controller does not allow the execution of the firmware code.

Abstract: An access device includes a memory controller coupled to a memory device and configured to access the memory device. The memory controller is further configured to perform a test procedure on the memory device to obtain a test result, write a boot code index, which indicates a predetermined address for storing predetermined system data of the memory device and a copy rule adopted for generating one or more duplicates of the predetermined system data, in the memory device, establish system data of the memory device according to the test result, write the system data into the predetermined address as the predetermined system data, and write the system data in one or more memory blocks of the memory device as the duplicates of the predetermined system data according to the copy rule.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing an enabling signal to an output device, where the flash controller and the output device are disposed on a printed circuit board (PCB) and intercoupled through wires in the PCB; reading an opcode of the reliable command corresponding to a flash module from the output device, where the flash module is disposed on the PCB and coupled to the flash controller through circuits in the PCB, and the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode; and stopping issuing the enabling signal to the output device after obtaining the opcode of the reliable command.

Abstract: The invention introduces a non-transitory computer program product for activating a flash device when executed by a processing unit of the flash device to have program code to: determine whether the flash device is physically reset when the flash device enters a test mode perform an operation of a first phase for transmitting a very first message to a card-initialization host when the flash device is physically reset; and perform an operation of a second phase for searching a flash module for information referenced by In-System Programming (ISP) code, obtaining the ISP code from a designated address, and programming the ISP code into the flash module when the flash device is not physically reset.