Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: A programmable testing apparatus imposes power interruptions on a storage device at any given point of time under at least one workload according to at least one protocol for tests. The programmable testing apparatus includes a controller unit connected to a workload unit, a power control unit, a protocol control unit and a data buffer unit. The controller unit calculates and receives and replies commands in the tests. The workload unit imposes various workloads on the storage device. The power control unit imposes power interruptions on the storage device under control of the controller unit. The protocol control unit provides commands according to the protocol for tests. The data buffer unit stores critical data and information to check whether data stored in the storage device are correct.

Abstract: An apparatus for measuring power of a PCIe device in various modes under the control of a testing host includes two PCIe bus ports, a microcontroller unit, a current-measuring unit and a switch unit. In operation, the first PCIe bus port is electrically connected to the testing host, and the second PCIe bus port is electrically connected to the PCIe device. The microcontroller unit receives commands from and sends signals to the testing host via the first PCIe bus port. The current-measuring unit is in communication of electricity and signals with the second PCIe bus port and electrically connected to the microcontroller unit. The current-measuring unit includes large and small current-measuring paths. The switch unit includes two switches. Under the control of the microcontroller unit, the current-measuring unit is electrically connected to the first PCIe bus port via the large or small current-measuring path and the first or second switch.

Abstract: A programmable testing apparatus imposes power interruptions on a storage device at any given point of time under at least one workload according to at least one protocol for tests. The programmable testing apparatus includes a controller unit connected to a workload unit, a power control unit, a protocol control unit and a data buffer unit. The controller unit calculates and receives and replies commands in the tests. The workload unit imposes various workloads on the storage device. The power control unit imposes power interruptions on the storage device under control of the controller unit. The protocol control unit provides commands according to the protocol for tests. The data buffer unit stores critical data and information to check whether data stored in the storage device are correct.

Abstract: A programmable testing apparatus imposes power interruptions on a storage device at any given point of time under at least one workload according to at least one protocol for tests. The programmable testing apparatus includes a controller unit connected to a workload unit, a power control unit, a protocol control unit and a data buffer unit. The controller unit calculates and receives and replies commands in the tests. The workload unit imposes various workloads on the storage device. The power control unit imposes power interruptions on the storage device under control of the controller unit. The protocol control unit provides commands according to the protocol for tests. The data buffer unit stores critical data and information to check whether data stored in the storage device are correct.

Abstract: An apparatus for measuring power of a PCIe device in various modes under the control of a testing host includes two PCIe bus ports, a microcontroller unit, a current-measuring unit and a switch unit. In operation, the first PCIe bus port is electrically connected to the testing host, and the second PCIe bus port is electrically connected to the PCIe device. The microcontroller unit receives commands from and sends signals to the testing host via the first PCIe bus port. The current-measuring unit is in communication of electricity and signals with the second PCIe bus port and electrically connected to the microcontroller unit. The current-measuring unit includes large and small current-measuring paths. The switch unit includes two switches. Under the control of the microcontroller unit, the current-measuring unit is electrically connected to the first PCIe bus port via the large or small current-measuring path and the first or second switch.

Abstract: An optimized high-speed sorter has a plurality of process elements connected in series. Each process element includes a sorting unit used to store a sorted item, and a comparing/controlling unit coupled to the sorting unit. In this sorter, all sorted items are compared with the input item simultaneously, and then are divided into an LE-group wherein the sorted items are less than or equal to the input item, and a G-group wherein the sorted items are greater than the input item. We assume that the sorted items are arranged in a descending sequence from left to right. In the insertion operation, the sorted items in the LE-group are shifted rightwards simultaneously, and the input item is loaded in the position between the LE-group and G-group. In the deletion operation, only the sorted items in the LE-group are shifted leftwards simultaneously. In order to accelerate the operation speed, the sorter adopts a pre-shift strategy.