Abstract: A semiconductor processing system is provided. The semiconductor processing system includes a first chamber arranged to perform a first semiconductor process; a second chamber arranged to perform a second semiconductor process; a cooling chamber having a pedestal; and a plurality of non-contact temperature sensors mounted in the cooling chamber, and arranged to measure a temperature of a wafer disposed on the pedestal. In one aspect, the first chamber is arranged to transfer the wafer to the cooling chamber upon completion of the first semiconductor process in the first chamber. In another aspect, the cooling chamber is arranged to measure the temperature of the wafer in the cooling chamber and arranged to transfer the wafer to the second chamber when the temperature of wafer is at a target temperature, or pause processing of the wafer when the temperature of the wafer is not at the target temperature.

Abstract: The present invention relates to a decorative panel designed for assembly on an outlet or a switch unit. The outlet includes multiple body slots, and the decorative panel comprises multiple slot reserved holes, each corresponding to one of the body slots. The surface of the decorative panel is seamless and flat. This decorative panel easily integrates into various interior design styles, offering an aesthetic solution that combines functionality with modern decor preferences.

Abstract: A sputtering target assembly, sputtering apparatus, and method, the target assembly including a backing plate having an aperture formed therein; and a target bonded to a front surface of the backing plate. The aperture is disposed on the backing plate such that a first end of the aperture is sealed by a portion of the target that is predicted by a sputtering target erosion profile to have the highest etching rate during a corresponding sputtering process.

Abstract: A sputtering target assembly, sputtering apparatus, and method, the target assembly including a backing plate having an aperture formed therein; and a target bonded to a front surface of the backing plate. The aperture is disposed on the backing plate such that a first end of the aperture is sealed by a portion of the target that is predicted by a sputtering target erosion profile to have the highest etching rate during a corresponding sputtering process.

Abstract: A sputtering target assembly, sputtering apparatus, and method, the target assembly including a backing plate having an aperture formed therein; and a target bonded to a front surface of the backing plate. The aperture is disposed on the backing plate such that a first end of the aperture is sealed by a portion of the target that is predicted by a sputtering target erosion profile to have the highest etching rate during a corresponding sputtering process.

Abstract: In an embodiment, a system includes: a chamber; and a magnetic assembly contained within the chamber. The magnetic assembly comprises: an inner magnetic portion comprising first magnets; and an outer magnetic portion comprising second magnets. At least two adjacent magnets, of either the first magnets or the second magnets, have different vertical displacements, and the magnetic assembly is configured to rotate around an axis to generate an electromagnetic field that moves ions toward a target region within the chamber.

Abstract: A sputtering target assembly, sputtering apparatus, and method, the target assembly including a backing plate having an aperture formed therein; and a target bonded to a front surface of the backing plate. The aperture is disposed on the backing plate such that a first end of the aperture is sealed by a portion of the target that is predicted by a sputtering target erosion profile to have the highest etching rate during a corresponding sputtering process.

Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

Abstract: A field effect transistor is manufactured by firstly forming an epitaxial layer on a substrate. Then, a trench having an oxide layer is formed on the epitaxial layer. The oxide layer has a first electrode portion having a first width and a first height and a second electrode portion having a second width and a second height. A gate oxide layer covering the oxide layer and the second electrode portion has a gate portion having a third width. The epitaxial layer has a body region and a source region, where these two regions are adjacent to the gate portion and covered by an interlayer dielectric. A source electrode covering the body region and the interlayer dielectric contacts the source region. The first height is no less than the second height, the first width is smaller than the second width, and the second width is smaller than the third width.

Abstract: A field effect transistor is manufactured by firstly forming an epitaxial layer on a substrate. Then, a trench having an oxide layer is formed on the epitaxial layer. The oxide layer has a first electrode portion having a first width and a first height and a second electrode portion having a second width and a second height. A gate oxide layer covering the oxide layer and the second electrode portion has a gate portion having a third width. The epitaxial layer has a body region and a source region, where these two regions are adjacent to the gate portion and covered by an interlayer dielectric. A source electrode covering the body region and the interlayer dielectric contacts the source region. The first height is no less than the second height, the first width is smaller than the second width, and the second width is smaller than the third width.

Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

Abstract: A method for manufacturing a field effect transistor having a widened trench forms sequentially an epitaxial layer, a trench, an oxidation layer, a trench-oxidation layer, a polysilicon layer, a residual oxidation layer, an electrode portion, a lower trench, a widened trench, a gate portion, a body region, a source region, an interlayer dielectric layer and a source electrode. The trench is formed at the epitaxial layer. The oxidation layer, the trench-oxidation layer and a polysilicon layer are then formed. The residual oxidation layer and the electrode portion are formed in the trench by etching the polysilicon layer and the trench-oxidation layer. The lower trench is formed by etching the epitaxial layer. The widened trench is formed by widening a portion of the trench away from a trench bottom so as to have the electrode portion and the residual oxidation layer disposed at the lower trench.