Abstract: A method for applying photoresist on a wafer is disclosed. The method comprises: lowering the temperature of the photoresist, and dispensing the photoresist on a portion of the wafer, where the wafer is supported by a spinner chuck and is rotated at a low speed. Thereafter, spreading the photoresist on the wafer by rotating the wafer at a high speed. Finally, planarizing the photoresist by rotating the wafer at a medium speed greater than or equal to the low speed in the dispensing step and less than or equal to the high speed in the spreading step.

Abstract: A process and a monitor structure to measure semiconductor device dimensions, especially contact and via hole dimensions, and proximity effects. The monitor has structures and layers which match the thickness and configuration of the product devices and allow measurement of step heights and proximity measurements. The monitor pattern includes an alignment region for use with automeasurement equipment. Measurements of openings are performed on the monitor at various points during the fabrication process.

Abstract: A method is disclosed which eliminates standing waves in the photoresist layer of VLSI devices. A layer of anti-reflecting material is deposited between the photoresist and its underlying poly layer. This anti-reflecting layer is formed with an appropriate thickness and index of refraction so that none of the lithographic light incident on the photoresist is reflected back from the underlying layer. This eliminates the interference between incident and reflected light in the photoresist, thus preventing the occurrence of standing waves.

Abstract: A new method of forming device isolation regions on a silicon substrate is provided. This method comprises the following steps: a pad oxide layer is formed on the silicon substrate; a silicon nitride layer is formed on the pad oxide layer; portions of the silicon nitride and pad oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions; silicon nitride spacers are formed on the sidewalls of the trenches; a first field oxide layer is grown on bottoms of the trenches by using thermal oxidation wherein a thin oxide layer is also formed on the silicon nitride layer; the thin oxide layer, silicon nitride layer, silicon nitride spacers and pad oxide layer are removed, respectively; and a second field oxide layer is formed on the first field oxide layer by using liquid phase deposition so as to fill all of the trenches.

Abstract: A method of forming a metallurgy system on a semiconductor substrate is provided. A first conformal layer of SiO.sub.2 is deposited on the substrate using plasma enhanced chemical vapor deposition (PECVD) techniques. Subsequently a non-conformal organic layer is deposited by spin-on-glass (SOG) techniques over the first layer, and heated to smoothen the surface. The organic SOG deposited layer is then subjected to a N.sub.2 plasma environment and a second conformal layer of SiO.sub.2 is deposited, and then vias etched through the layers. The resist layer used to define vias is removed by an O.sub.2 plasma and the device metallurgy completed.