Abstract: A terminal for handling data in a live streaming platform, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: requesting event-related data from the live streaming platform; and determining cache strategy according to timing of the progress of the event. According to the above embodiments, the cache strategy may be determined dynamically before, during and after an event. The Server load may be reduced and the responsiveness of the user terminal may also be improved. The auto-switching cache strategy may also minimize potential user misunderstandings. Therefore, the user experience may be improved.

Abstract: A terminal for handling data in a live streaming platform, including one or a plurality of processors, wherein the one or plurality of processors execute a machine- readable instruction to perform: transmitting a request on a portion of data; receiving a response of the request; setting a retry count in response to the response being failed and the portion of data being not the first portion; determining retry time according to the set retry count; and transmitting a next request on the portion of data after the retry time. According to the present disclosure, the requested data, such as the leaderboard data, may be displayed smoothly to the user terminal regardless of the network condition, rather than showing a blank screen. Therefore, the user experience may be improved.

Abstract: This disclosure relates to a combination structure of an output line and a terminal. An output line includes an insulation sleeve and a copper wire. A conducting terminal includes a riveting ring, a conducting ring and a soldering segment connected to one another. The riveting ring is fixed on the insulation sleeve. The conducting ring covers the copper wire. The soldering segment is bent and extended with an included angle with respect to an extending direction of the output line. The output line and the conducting terminal pass through a reflow oven to make the conducting ring and the copper wire be tinned and connected. The insulation seat includes a base and a terminal slot. The soldering segment is embedded in the terminal slot. The circuit board and the conducting terminal pass through the reflow oven to make the soldering segment be tinned and connected to the circuit board.

Abstract: A planar transformer includes: a first primary winding layer; a second primary winding layer disposed adjacent to the first primary winding layer; a shielding layer disposed adjacent to the first primary winding layer; a first secondary winding layer disposed adjacent to the shielding layer; a second secondary winding layer disposed adjacent to the first secondary winding layer. The first primary winding layer and the second primary winding layer are located at one side of the shielding layer. The first secondary winding layer and the second secondary winding layer are located at another side of the shielding layer.

Abstract: A thin-film transistor includes a substrate, a first thin-film structure, a gate structure, and a second thin-film structure that are sequentially disposed on one another. The first thin-film structure includes a channel layer, and first source and drain layers disposed at opposite sides of the channel layer. The gate structure includes a common gate electrode disposed on the channel layer, and a gate insulating layer wrapping the common gate electrode and covering the first thin-film structure. The second thin-film structure includes an active layer disposed on the gate insulating layer and including an indium oxide-based material, and second source and drain layers disposed at opposite sides of the active layer.

Abstract: The present invention discloses a manufacturing method of a semiconductor component with a nanowire channel. The method comprises the following steps. The step of forming a stack structure on a substrate is performed. A semiconductor layer is formed on the substrate and the stack structure and further filled into the fillister. The semiconductor layer is patterned to form a source area and a drain area, and the channel region is located between the source area and the drain area. The semiconductor layer located outside the source area, the drain area and the fillister will be removed. And then, the stack structure is then removed. Therefore, the semiconductor layer filled inside the fillister will be exposed to be as a channel. A gate oxide layer is formed to cover the channel, and a gate layer is then formed on the gate oxide layer.