Abstract: A method of backlight control for a display panel is provided. The display panel is configured to display with a variable refresh rate in a plurality of frame periods each having a fixed period and a variable period. The method includes steps of: generating a first backlight control signal in the fixed period of a frame period; determining whether a liquid crystal (LC) transition time corresponding to the frame period ends before an end time of the variable period of the frame period; generating a second backlight control signal in the variable period of the frame period when the LC transition time ends before the end time of the variable period of the frame period; and generating a compensation backlight control signal in a next frame period according to a backlight duty cycle of the frame period.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: An optical probe package structure is provided, used in a test environment for testing a plurality of optical chips on a wafer, including: a main body, an optical fiber, an optical fiber positioning area, a mode field conversion waveguide structure, and an optical waveguide. Wherein, the mode field conversion waveguide structure is used to convert the propagation field of the optical signal, and the optical signal transmitted by the mode field conversion waveguide structure enters the optical waveguide. The optical waveguide has an emitting end, and the emitting end is provided with a facet, the facet has a facet angle, and the facet angle makes the optical signal after field conversion mode field conversion to produce total reflection and output along a second direction. The optical signal after total reflection enters the optical chips. Thereby, an optical probe package structure that can test before wafer cutting and polishing is provided.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: An assembly alignment structure for optical component is provided, including: an optical fiber, comprising: a combined fiber segment and a plurality of bare fiber segments; a cover plate, having a first installation surface disposed with a plurality of guide grooves, an installation groove, and at least one first coupling groove, the bare fiber segments being in the corresponding in the guide grooves; a lens, arranged in the installation groove; a chip, having a signal receiving surface; a carrier plate, having a second installation surface disposed with at least one second coupling groove, the chip is fixed on the second installation surface; and at least one positioning post; when the cover plate and carrier plate are aligned, the positioning post is located in the first and second coupling grooves, and the optical fiber and the lens are fixed and aligned between the carrier plate and the cover plate.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.

Abstract: An alignment structure of optical element is provided, including: an optical fiber, having a parallel fiber segment and a plurality of bare fiber segments; a cover plate, provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped; and a silicon chip, provided with lines and a plurality of second coupling parts; when the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts being coupled and positioned with each other respectively, and the optical fiber being fixed between the silicon chip and the cover plate. As such, precise positioning and rapid assembly are achieved.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: An optical probe package structure is provided, used in a test environment for testing a plurality of optical chips on a wafer, including: a main body, an optical fiber, an optical fiber positioning area, a mode field conversion waveguide structure, and an optical waveguide. Wherein, the mode field conversion waveguide structure is used to convert the propagation field of the optical signal, and the optical signal transmitted by the mode field conversion waveguide structure enters the optical waveguide. The optical waveguide has an emitting end, and the emitting end is provided with a facet, the facet has a facet angle, and the facet angle makes the optical signal after field conversion mode field conversion to produce total reflection and output along a second direction. The optical signal after total reflection enters the optical chips. Thereby, an optical probe package structure that can test before wafer cutting and polishing is provided.

Abstract: An optical probe for optoelectronic integrated circuits is provided, applicable to a test environment for testing a plurality of optical chips on a wafer. The optical chips include at least one optical waveguide, and the optical probe includes a substrate and an optical fiber. The facet of the optical fiber has a first angle, and the first angle causes the optical signal transmitted by the optical fiber to generate total reflection, and the optical signal after total reflection enters the optical waveguide of the optical chip. Thereby, an optical probe able to perform testing before wafer cutting and polishing is provided, and a high-speed, effective and reliable detection is achieved.

Abstract: An optical probe for optoelectronic integrated circuits is provided, applicable to a test environment for testing a plurality of optical chips on a wafer. The optical chips include at least one optical waveguide, and the optical probe includes a substrate and an optical fiber. The facet of the optical fiber has a first angle, and the first angle causes the optical signal transmitted by the optical fiber to generate total reflection, and the optical signal after total reflection enters the optical waveguide of the optical chip. Thereby, an optical probe able to perform testing before wafer cutting and polishing is provided, and a high-speed, effective and reliable detection is achieved.

Abstract: An alignment structure of optical element is provided, including: an optical fiber, having a parallel fiber segment and a plurality of bare fiber segments; a cover plate, provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped; and a silicon chip, provided with lines and a plurality of second coupling parts; when the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts being coupled and positioned with each other respectively, and the optical fiber being fixed between the silicon chip and the cover plate. As such, precise positioning and rapid assembly are achieved.

Abstract: A deepfake video detection system, including an input data detection module of a video recognition unit for setting a target video; a data pre-processing unit for detecting eye features from the face in the target video; a feature extraction module for extracting eye features and inputting the eye features to a long-term recurrent convolutional neural network (LRCN); and then using a sequence of long-term and short-term memory (LSTM) of a learning module; performing sequence learning; using a state prediction module to predict the output of each neuron, and then using a long and short-term memory model to output the quantized eye state, then connecting to a state quantification module, and comparing the original stored data from the normal video and the quantified eye state information of the target video, and outputting the recognition result by an output data recognition module.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Abstract: A training system and method of object detection model is disclosed. The training system includes an object detection model and a loss calculation module. The object detection model is configured to generate an output image according to an input image. The loss calculation module, coupled to the object detection model, is configured to calculate a total classification loss value according to the output image and a solution image, calculate a loss value according to the total classification loss value, and transmit the loss value to the object detection model. The total classification loss value is calculated according to a number of classification losses corresponding to a number of object types. Each classification loss corresponding to each object type is calculated according to a first parameter, a second parameter and a third parameter.

Abstract: A deepfake video detection system, including an input data detection module of a video recognition unit for setting a target video; a data pre-processing unit for detecting eye features from the face in the target video; a feature extraction module for extracting eye features and inputting the eye features to a long-term recurrent convolutional neural network (LRCN); and then using a sequence of long-term and short-term memory (LSTM) of a learning module; performing sequence learning; using a state prediction module to predict the output of each neuron, and then using a long and short-term memory model to output the quantized eye state, then connecting to a state quantification module, and comparing the original stored data from the normal video and the quantified eye state information of the target video, and outputting the recognition result by an output data recognition module.

Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.