Abstract: A control device for a power switch, a control method for the power switch, and an electronic display system are provided. The control device includes an acoustic sensor and a switch. The switch is coupled between a power supply and an external electronic device. The acoustic sensor senses an acoustic signal. In a standby mode, the acoustic sensor generates a switch control signal according to a frequency of the acoustic signal. The switch turns on or turns off a path for the external electronic device to receive power according to the switch control signal. In the standby mode, the acoustic sensor periodically and actively performs a generating operation of the switch control signal.

Abstract: An assembly alignment structure for optical component includes an optical fiber comprising a combined fiber segment and a plurality of bare fiber segments; a cover plate having a first installation surface disposed with a plurality of guide grooves, an installation groove, and at least one first coupling groove, the bare fiber segments being in the corresponding in the guide grooves; a lens arranged in the installation groove; a chip having a signal receiving surface; a carrier plate having a second installation surface disposed with at least one second coupling groove, the chip being fixed on the second installation surface; and at least one positioning post. When the cover plate and carrier plate are aligned, the positioning post is located in the first and second coupling grooves, and the optical fiber and the lens are fixed and aligned between the carrier plate and the cover plate.

Abstract: An assembly alignment structure for optical component includes an optical fiber, comprising: a combined fiber segment and a plurality of bare fiber segments; a cover plate, having a first installation surface disposed with a plurality of guide grooves, an installation groove, and at least one first coupling groove, the bare fiber segments being in the corresponding in the guide grooves; a lens, arranged in the installation groove; a chip, having a signal receiving surface; a carrier plate, having a second installation surface disposed with at least one second coupling groove, the chip being fixed on the second installation surface; and at least one positioning post; wherein when the cover plate and carrier plate are aligned, the positioning post is located in the first and second coupling grooves, and the optical fiber and the lens are fixed and aligned between the carrier plate and the cover plate.

Abstract: The present invention provides an optical interposer for chip connection including a first total internal reflective layer, a waveguide and a second total internal reflective layer. The optical interposer is disposed above a first photonic integrated circuit chip and a second photonic integrated circuit chip, coupling the first photonic integrated circuit chip and the second photonic integrated circuit chip. The refractive indices of the first total internal reflective layer and the second total internal reflective layer are lower than the waveguide, making a light signal perform repetitive total internal reflections at the junctions between materials and advance in a zigzag shape within the waveguide, and further transmits between the first photonic integrated circuit chip and the second photonic integrated circuit chip.

Abstract: A pluggable optical packaging structure is provided, including: a substrate, a carrier ring, at least one optical connection assembly and a cover plate; the substrate includes at least one electronic integrated circuit (EIC) and at least one photonic integrated circuit (PIC); the carrier ring is located on the substrate, and the EIC and PIC are enclosed by the carrier ring; the optical connection assembly includes at least one socket, at least one connector, a plurality of optical fibers and at least one optical fiber array connector, the socket is located in a partial section of the carrier ring, the connector is in the socket, the optical fibers has one end coupled to the connector, the other end coupled to the fiber array connector, and is coupled to the PIC through the fiber array connector; the cover plate is located on the carrier ring and extends inwardly to above the PIC.

Abstract: A light-coupling device includes an interposer, an optical chip, an optical waveguide element and a fiber array connector. The optical chip includes a waveguide layer with a light-emitting surface located aside the optical chip. The optical waveguide element includes an incident surface facing the light-emitting surface, an emergent surface located atop, and a reflective surface located inside. A light beam emitted horizontally from the light-emitting surface enters the optical waveguide element through the incident surface, totally reflected through the reflective surface and is output as a parallel light beam in the vertical direction through the emergent surface. The fiber array connector includes an optical waveguide lens and a plurality of fibers. The optical waveguide lens faces the emergent surface. One of both horizontal sides of the optical waveguide lens is a tilted reflective surface while the other is a light-coupling surface aligned with the fibers.

Abstract: The present invention provides a semiconductor structure including a substrate, a metal reflective layer, a UV glue layer, and an element. The metal reflective layer is placed on the surface of the substrate, and the UV glue layer is placed on the surface of the metal reflective layer. The element is manufactured by light-transparent material. The UV glue layer adheres the element to the metal reflective layer. By so, in the light-curing process, the curing of the UV glue is accelerated due to the metal reflective layer reflecting an ultraviolet ray.

Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.

Abstract: An alignment structure of an optical element includes an optical fiber having a parallel fiber segment and a plurality of bare fiber segments, a cover plate provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped, and a silicon chip provided with lines and a plurality of second coupling parts. When the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts are coupled and positioned with each other respectively, and the optical fiber is fixed between the silicon chip and the cover plate.

Abstract: An optical probe package structure is provided, used in a test environment for testing a plurality of optical chips on a wafer, including: a main body, an optical fiber, an optical fiber positioning area, a mode field conversion waveguide structure, and an optical waveguide. Wherein, the mode field conversion waveguide structure is used to convert the propagation field of the optical signal, and the optical signal transmitted by the mode field conversion waveguide structure enters the optical waveguide. The optical waveguide has an emitting end, and the emitting end is provided with a facet, the facet has a facet angle, and the facet angle makes the optical signal after field conversion mode field conversion to produce total reflection and output along a second direction. The optical signal after total reflection enters the optical chips. Thereby, an optical probe package structure that can test before wafer cutting and polishing is provided.

Abstract: An assembly alignment structure for optical component is provided, including: an optical fiber, comprising: a combined fiber segment and a plurality of bare fiber segments; a cover plate, having a first installation surface disposed with a plurality of guide grooves, an installation groove, and at least one first coupling groove, the bare fiber segments being in the corresponding in the guide grooves; a lens, arranged in the installation groove; a chip, having a signal receiving surface; a carrier plate, having a second installation surface disposed with at least one second coupling groove, the chip is fixed on the second installation surface; and at least one positioning post; when the cover plate and carrier plate are aligned, the positioning post is located in the first and second coupling grooves, and the optical fiber and the lens are fixed and aligned between the carrier plate and the cover plate.

Abstract: An alignment structure of optical element is provided, including: an optical fiber, having a parallel fiber segment and a plurality of bare fiber segments; a cover plate, provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped; and a silicon chip, provided with lines and a plurality of second coupling parts; when the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts being coupled and positioned with each other respectively, and the optical fiber being fixed between the silicon chip and the cover plate. As such, precise positioning and rapid assembly are achieved.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: An optical probe package structure is provided, used in a test environment for testing a plurality of optical chips on a wafer, including: a main body, an optical fiber, an optical fiber positioning area, a mode field conversion waveguide structure, and an optical waveguide. Wherein, the mode field conversion waveguide structure is used to convert the propagation field of the optical signal, and the optical signal transmitted by the mode field conversion waveguide structure enters the optical waveguide. The optical waveguide has an emitting end, and the emitting end is provided with a facet, the facet has a facet angle, and the facet angle makes the optical signal after field conversion mode field conversion to produce total reflection and output along a second direction. The optical signal after total reflection enters the optical chips. Thereby, an optical probe package structure that can test before wafer cutting and polishing is provided.

Abstract: An optical probe for optoelectronic integrated circuits is provided, applicable to a test environment for testing a plurality of optical chips on a wafer. The optical chips include at least one optical waveguide, and the optical probe includes a substrate and an optical fiber. The facet of the optical fiber has a first angle, and the first angle causes the optical signal transmitted by the optical fiber to generate total reflection, and the optical signal after total reflection enters the optical waveguide of the optical chip. Thereby, an optical probe able to perform testing before wafer cutting and polishing is provided, and a high-speed, effective and reliable detection is achieved.

Abstract: An optical probe for optoelectronic integrated circuits is provided, applicable to a test environment for testing a plurality of optical chips on a wafer. The optical chips include at least one optical waveguide, and the optical probe includes a substrate and an optical fiber. The facet of the optical fiber has a first angle, and the first angle causes the optical signal transmitted by the optical fiber to generate total reflection, and the optical signal after total reflection enters the optical waveguide of the optical chip. Thereby, an optical probe able to perform testing before wafer cutting and polishing is provided, and a high-speed, effective and reliable detection is achieved.

Abstract: An alignment structure of optical element is provided, including: an optical fiber, having a parallel fiber segment and a plurality of bare fiber segments; a cover plate, provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped; and a silicon chip, provided with lines and a plurality of second coupling parts; when the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts being coupled and positioned with each other respectively, and the optical fiber being fixed between the silicon chip and the cover plate. As such, precise positioning and rapid assembly are achieved.

Abstract: A deepfake video detection system, including an input data detection module of a video recognition unit for setting a target video; a data pre-processing unit for detecting eye features from the face in the target video; a feature extraction module for extracting eye features and inputting the eye features to a long-term recurrent convolutional neural network (LRCN); and then using a sequence of long-term and short-term memory (LSTM) of a learning module; performing sequence learning; using a state prediction module to predict the output of each neuron, and then using a long and short-term memory model to output the quantized eye state, then connecting to a state quantification module, and comparing the original stored data from the normal video and the quantified eye state information of the target video, and outputting the recognition result by an output data recognition module.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.