Abstract: A Reliability, Availability and Serviceability (RAS) offload Post-Package Repair (PPR) request system includes a memory system coupled to a Baseboard Management Controller (BMC) device and a Basic Input/Output System (BIOS) subsystem. The BMC device identifies an error in the memory system, retrieves error information associated with the error, uses the error information to generate a Post-Package Repair (PPR) request, and stores the PPR request in a BMC database provided in the BMC device. During an initialization process that occurs subsequent to storing the PPR request in the BMC database, the BMC device retrieves the PPR request and stores it in a shared buffer subsystem. During the initialization process, the BIOS retrieves the PPR request from the shared buffer subsystem, stores the PPR request in a BIOS database provided in the BIOS subsystem, and performs PPR operations on the memory system based on the PPR request stored in the BIOS database.

Abstract: A BIOS code storage subsystem modification system includes a computing device having BIOS code storage device modification subsystem coupled to a BIOS storage system that includes a BIOS code storage device and a BIOS data storage device. The BIOS code storage device modification subsystem receives a BIOS code storage device modification interrupt and, in response, provides BIOS code storage device modification information in the BIOS data storage device. Subsequent to providing the BIOS code storage device modification information in the BIOS data storage device, the BIOS code storage device modification subsystem causes the computing device to perform a first reboot. During a first initialization of the computing device in response to the first reboot, a BIOS in the computing device identifies the BIOS code storage device modification information in the BIOS data storage device, and uses the BIOS code storage device modification information to modify the BIOS code storage device.

Abstract: A BIOS module provisioning sequence verification system includes a BIOS subsystem coupled to a TPM and a BIOS storage system including a plurality of firmware volumes. The BIOS subsystem provides a plurality of BIOS modules in a BIOS module provisioning sequence using the plurality of firmware volumes and, for each of the plurality of BIOS modules when that BIOS module is provided during the BIOS module provisioning sequence: retrieves a BIOS module identifier associated with that BIOS module, and updates BIOS module provisioning sequence information using that BIOS module identifier. Following the provisioning of the BIOS modules in the BIOS module provisioning sequence, the BIOS subsystem provides the BIOS module provisioning sequence information to the TPM, with the BIOS module provisioning sequence information configured to be compared to BIOS module provisioning sequence verification information to verify the BIOS module provisioning sequence.

Abstract: An embodiment of the invention provides a material recognition system. The material recognition system may include a fetching device, at least one sensing device and a processing device. The fetching device may fetch a target object. Each sensing device may include an ultrasound transmitter and an ultrasound receiver. The ultrasound transmitter may transmit an ultrasound emitting signal on the surface of the target object. The ultrasound receiver may receive an ultrasound received signal on the surface of the target object. There is a fixed distance between the ultrasound transmitter and the ultrasound receiver. The processing device may recognize the material of the target object according to the ultrasound emitting signal, the ultrasound received signal, and the fixed distance. In addition, when the fetching device fetches the target object, the ultrasound transmitter and the ultrasound receiver touch the surface of the target object.

Abstract: A BIOS backup/recovery system includes a chassis housing a BIOS backup/recovery subsystem coupled to a primary and a secondary BIOS storage system. The BIOS backup/recovery subsystem begins initialization operations and determines whether the primary BIOS storage system includes customized MAC addresses. If so, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match the customized MAC addresses in the primary BIOS storage system and, if not, performs a BIOS backup operation that includes copying the customized MAC addresses in the primary BIOS storage system to the secondary BIOS storage system. If not, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match default MAC addresses in the primary BIOS storage system and, if not, performs a BIOS recovery operation that includes copying customized MAC addresses in the secondary BIOS storage system to the primary BIOS storage system.

Abstract: A UEFI variable storage system includes a UEFI variable services subsystem coupled to UEFI variable sources, a trusted UEFI variable storage subsystem, and an untrusted UEFI variable storage subsystem. If the UEFI variable services subsystem receives a first UEFI variable during a first UEFI initialization process from a first UEFI variable source and determines that the first UEFI initialization process has not reached an untrusted UEFI variable source point, it stores the first UEFI variable in the trusted UEFI variable storage subsystem. If the UEFI variable services subsystem receives a second UEFI variable during the first UEFI initialization process from a second UEFI variable source and determines that the first UEFI initialization process has reached the untrusted UEFI variable source point, it stores the second UEFI variable in the untrusted UEFI variable storage subsystem.

Abstract: A BIOS module provisioning sequence verification system includes a BIOS subsystem coupled to a TPM and a BIOS storage system including a plurality of firmware volumes. The BIOS subsystem provides a plurality of BIOS modules in a BIOS module provisioning sequence using the plurality of firmware volumes and, for each of the plurality of BIOS modules when that BIOS module is provided during the BIOS module provisioning sequence: retrieves a BIOS module identifier associated with that BIOS module, and updates BIOS module provisioning sequence information using that BIOS module identifier. Following the provisioning of the BIOS modules in the BIOS module provisioning sequence, the BIOS subsystem provides the BIOS module provisioning sequence information to the TPM, with the BIOS module provisioning sequence information configured to be compared to BIOS module provisioning sequence verification information to verify the BIOS module provisioning sequence.

Abstract: A BIOS update system includes a BIOS update subsystem that is coupled to a memory system and a BIOS. The BIOS update subsystem receives a BIOS update instruction and, in response, provides a BIOS update identifier in a non-volatile storage device that is accessible to the BIOS, provides a UEFI variable for the BIOS that identifies a location of BIOS update information in a storage device that is coupled to the BIOS update subsystem, and then causes a first reboot. Subsequent to the first reboot, the BIOS update subsystem identifies the BIOS update identifier in the non-volatile storage device and, in response, uses the location of the BIOS update information in the storage device identified by the UEFI variable to retrieve the BIOS update information. The BIOS update subsystem then updates the BIOS using the BIOS update information, and then causes a second reboot.

Abstract: A BIOS backup/recovery system includes a chassis housing a BIOS backup/recovery subsystem coupled to a primary and a secondary BIOS storage system. The BIOS backup/recovery subsystem begins initialization operations and determines whether the primary BIOS storage system includes customized MAC addresses. If so, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match the customized MAC addresses in the primary BIOS storage system and, if not, performs a BIOS backup operation that includes copying the customized MAC addresses in the primary BIOS storage system to the secondary BIOS storage system. If not, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match default MAC addresses in the primary BIOS storage system and, if not, performs a BIOS recovery operation that includes copying customized MAC addresses in the secondary BIOS storage system to the primary BIOS storage system.

Abstract: A secure boot policy may be stored in the information handling system and used to create a trusted relationship with a CPU, including a neutral CPU that has not been fused with an OEM key. The secure boot policy may be a data blob including platform-specific identification information (e.g., one or more of flash memory unique ID, motherboard ePPID), a boot policy (e.g., specifying to enable or disable neutral CPU fusing), and a signature. The secure boot policy may be stored in a one-time-programmable (OTP) storage of the information handling system, such as an OTP region in the serial peripheral interface (SPI) flash memory part storing the basic input/output system (BIOS). The BIOS may verify the secure boot policy using a public key and check if the boot policy is bound to current BIOS flash part and/or system configuration, and then apply the boot policy if the verification is passed.

Abstract: A secure boot policy may be stored in the information handling system and used to create a trusted relationship with a CPU, including a neutral CPU that has not been fused with an OEM key. The secure boot policy may be a data blob including platform-specific identification information (e.g., one or more of flash memory unique ID, motherboard ePPID), a boot policy (e.g., specifying to enable or disable neutral CPU fusing), and a signature. The secure boot policy may be stored in a one-time-programmable (OTP) storage of the information handling system, such as an OTP region in the serial peripheral interface (SPI) flash memory part storing the basic input/output system (BIOS). The BIOS may verify the secure boot policy using a public key and check if the boot policy is bound to current BIOS flash part and/or system configuration, and then apply the boot policy if the verification is passed.

Abstract: An early boot debug system includes a first memory subsystem that includes boot instructions and a processing system that is coupled to the first memory subsystem. The processing system includes a primary processing subsystem, and a secondary processing subsystem that is coupled to the primary processing subsystem and a second memory subsystem. The secondary processing subsystem copies the boot instructions from the first memory subsystem to the second memory subsystem and executes the boot instructions from the second memory subsystem during a boot operation. The secondary processing subsystem then detects a first event during the execution of the boot instructions and, in response, generates a first event information. The secondary processing subsystem stores the first event information in the second memory subsystem to be retrieved on-demand by an administrator.

Abstract: A protocol security system includes a protocol producer driver stored in a first memory range on a primary memory system, a protocol consumer driver stored on the primary memory system, and a firmware interface engine provided via the primary memory system. The firmware interface engine receives a protocol pointer from the protocol consumer driver, and identifies that the protocol pointer was provided by the protocol producer driver. If the firmware interface engine determines that the protocol pointer is not stored in the first memory range on the primary memory system, it generates a protocol security violation. If the firmware interface engine determines that the protocol pointer is stored in the first memory range on the primary memory system and points to an architectural protocol, it determines whether the protocol producer driver originated from a secondary memory system and, if not, generates a protocol security violation.

Abstract: A protocol security system includes a protocol producer driver stored in a first memory range on a primary memory system, a protocol consumer driver stored on the primary memory system, and a firmware interface engine provided via the primary memory system. The firmware interface engine receives a protocol pointer from the protocol consumer driver, and identifies that the protocol pointer was provided by the protocol producer driver. If the firmware interface engine determines that the protocol pointer is not stored in the first memory range on the primary memory system, it generates a protocol security violation. If the firmware interface engine determines that the protocol pointer is stored in the first memory range on the primary memory system and points to an architectural protocol, it determines whether the protocol producer driver originated from a secondary memory system and, if not, generates a protocol security violation.

Abstract: A initialization code/data memory mapping system includes a processing system, memory device(s) storing initialization code and initialization data, and a main memory system. The processing system performs first MMIO read operations to access the initialization code stored in the memory device(s) that is mapped to an initialization memory space in order to provide an initialization engine, and uses it to copy the initialization code from the memory device(s) to the main memory system. The processing system then accesses the initialization code stored in the main memory system in order to provide the initialization engine, and uses it to map the initialization data stored in the memory device(s) to the initialization memory space. The processing system then performs second MMIO read operations to access the initialization data stored in the memory device(s) that is mapped to the initialization memory space for use by the initialization engine.

Abstract: An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Abstract: An early boot debug system includes a first memory subsystem that includes boot instructions and a processing system that is coupled to the first memory subsystem. The processing system includes a primary processing subsystem, and a secondary processing subsystem that is coupled to the primary processing subsystem and a second memory subsystem. The secondary processing subsystem copies the boot instructions from the first memory subsystem to the second memory subsystem and executes the boot instructions from the second memory subsystem during a boot operation. The secondary processing subsystem then detects a first event during the execution of the boot instructions and, in response, generates a first event information. The secondary processing subsystem stores the first event information in the second memory subsystem to be retrieved on-demand by an administrator.

Abstract: An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Abstract: An electronic product including a supporting structure, a first thermo-formable film, a conductive circuit and a protection layer is provided. The conductive circuit is formed on the first thermo-formable film, and an electronic component is mounted on the conductive circuit. The protection layer covers the electronic component, and includes a second thermo-formable film. The conductive circuit and the electronic component are enclosed between the first thermo-formable film and the second thermo-formable film, and the supporting structure, the first thermo-formable film and the protection layer are bonded and stacked to each other.

Abstract: A syringe and needle assembly includes an elongated hollow barrel, a needle unit, and a plunger assembly. The hollow barrel has a connecting portion. The needle unit is disposed at the connecting portion and has an engaging structure, and the engaging structure is located in the hollow barrel. A plunger rod of the plunger assembly is movably disposed in the hollow barrel and has a pushing portion and an operating portion formed in front and rear ends of the plunger rod respectively, and the pushing portion faces the connecting portion and has a plurality of elastic hooks. The plunger assembly is adapted to move towards the connecting portion to push a liquid in the hollow barrel to be injected through a needle of the needle unit, and the plunger assembly is adapted to keep moving towards the connecting portion, such that the elastic hooks are engaged with the engaging structure.