Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.

Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.

Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.

Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.

Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.

Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.

Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.

Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.