Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: An integrated circuit includes a first and second conductor, and a first and second pair of transistors. The first conductor is on a back-side of a substrate, extending in a first direction, and being configured to supply a first supply voltage. The second conductor is on the back-side of the substrate, and extending in the first direction. The first pair of transistors includes a first gate extending in a second direction, overlapping at least the second conductor, being located on a first level of a front-side of the substrate opposite from the back-side. The second pair of transistors includes a second gate extending in the second direction, overlapping at least the second conductor, being on the first level, and being separated from the first gate in the first direction. The second conductor electrically couples the first gate and the second gate together.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active region extend in a first direction, and are on a first level. The first active region includes a first and second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact includes a first and second portion. The first portion overlaps the first and second drain/source. The second portion overlaps the first contact, the first and third drain/source region, and the first insulating region, and is electrically coupled to the first portion, and electrically insulated from the first drain/source region.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.

Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.

Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

Abstract: An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: An integrated circuit includes a first power rail, a second power rail, a signal line and a first active region of a first set of transistors. The first power rail is on a back-side of a substrate, and extends in a first direction. The second power rail is on the back-side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back-side of the substrate, and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first set of transistors extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side.

Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.