Patents by Inventor Pochun Wang

Pochun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569168
    Abstract: An integrated circuit includes a first power rail, a second power rail, a signal line and a first active region of a first set of transistors. The first power rail is on a back-side of a substrate, and extends in a first direction. The second power rail is on the back-side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back-side of the substrate, and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first set of transistors extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Pochun Wang, Wei-Hsin Tsai, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11550986
    Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Yu-Jung Chang, Hui-Zhong Zhuang, Ting-Wei Chiang
  • Publication number: 20220384598
    Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20220384414
    Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: CHENG-YU LIN, PO-HSIANG HUANG, POCHUN WANG, CHIH-LIANG CHEN, FONG-YUAN CHANG
  • Patent number: 11508661
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Publication number: 20220310598
    Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20220293638
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Inventors: POCHUN WANG, GUO-HUEI WU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, LI-CHUN TIEN
  • Patent number: 11362110
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pochun Wang, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11362090
    Abstract: A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20220067259
    Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: POCHUN WANG, JERRY CHANG JUI KAO, JUNG-CHAN YANG, HUI-ZHONG ZHUANG, TZU-YING LIN, CHUNG-HSING WANG
  • Patent number: 11188703
    Abstract: A method of forming an integrated circuit includes generating a first and a second standard cell layout design, generating a first set of cut feature layout patterns extending in a first direction, and manufacturing the integrated circuit based on the first or second standard cell layout design. Generating the first standard cell layout design includes generating a first set of conductive feature layout patterns extending in the first direction, and overlapping a first set of gridlines extending in the first direction. Generating the second standard cell layout design includes generating a second set of conductive feature layout patterns extending in the first direction and overlapping a second set of gridlines extending in the first direction. A side of a first cut feature layout pattern extending in the first direction is aligned with a first gridline of the first or second set of gridlines.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sang-Chi Huang, Hui-Zhong Zhuang, Jung-Chan Yang, Pochun Wang
  • Publication number: 20210358848
    Abstract: An integrated circuit includes a first power rail, a second power rail, a signal line and a first active region of a first set of transistors. The first power rail is on a back-side of a substrate, and extends in a first direction. The second power rail is on the back-side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back-side of the substrate, and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first set of transistors extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side.
    Type: Application
    Filed: March 9, 2021
    Publication date: November 18, 2021
    Inventors: Guo-Huei WU, Pochun WANG, Wei-Hsin TSAI, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20210279397
    Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Inventors: Pochun WANG, Yu-Jung CHANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG
  • Publication number: 20210242212
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Publication number: 20210242205
    Abstract: A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures.
    Type: Application
    Filed: September 22, 2020
    Publication date: August 5, 2021
    Inventors: Guo-Huei WU, Pochun WANG, Chih-Liang CHEN, Li-Chun TIEN
  • Patent number: 11048849
    Abstract: An integrated circuit includes a first active region, a second active region, a third active region, a first contact and a second contact. The first active region and the second active region are separated from each other in a first direction, and are located on a first level. The third active region is located on the first level and is separated from the second active region in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first contact and the third active region, is electrically coupled to the first contact, and is located on a third level different from the first level and the second level.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Hui-Zhong Zhuang, Yu-Jung Chang
  • Patent number: 11004855
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Publication number: 20210098500
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: July 13, 2020
    Publication date: April 1, 2021
    Inventors: POCHUN WANG, GUO-HUEI WU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, LI-CHUN TIEN
  • Publication number: 20200350250
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chih-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Ya-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Patent number: 10734321
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang