Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

Abstract: An LC (inductor-capacitor) tank includes a primary 8-shape inductor and a serial LC network that are connected in parallel across a first node and a second node and laid out using a multi-layer structure fabricated on a substrate, wherein a magnetic coupling between the primary 8-shape inductor and the serial LC network is mitigated due to a layout symmetry, and a resonant frequency of the serial LC network is equal to three times of a resonance frequency of the LC tank.

Abstract: Embodiments described herein provide circuitry employing one or more inductors having an unconventional turn-ratio. The circuitry includes a primary inductor having a first length located on a first layer of an integrated circuit (IC). The circuitry further includes a secondary inductor having a second length located on a second layer of the IC different from the first layer, whereby the second length is greater than the first length, with a ratio between the first and the second lengths corresponding to a non-integer turn-ratio.

Abstract: A radio transmitter includes a power amplifier configured to receive an input voltage signal and output an output voltage signal; a transformer configured to receive the output voltage signal and output a load voltage signal to a load; a sensing inductor configured to output a sensed current signal in accordance with a magnetic coupling with the transformer; a digitally controlled phase shifter configured to receive the output voltage signal and output a phase-shifted voltage signal in accordance with a phase control code; a mixer configured to output a mixed current signal in accordance with a mixing of the sensed current signal and the phase-shifted voltage signal; and a transimpedance amplifier with of a low-pass response configured to convert the mixed current signal into a mean voltage signal.

Abstract: A radio frequency integrated circuit includes a transmitter integrated on a die, the transmitter circuit being controlled by a first logical signal and configured to receive a to-be-transmitted signal and output a first voltage at a first internal node; a receiver integrated on the die. The receiver circuit is controlled by the first logical signal and a second logical signal and configured to output a receive signal. A first pad, a second pad, and a first inductor integrated on the die, the first pad being connected to the first internal node, the second pad being connected to the second internal node, and the first inductor being placed across the first internal node and the second internal node.

Abstract: A radio transmitter includes a power amplifier configured to receive an input voltage signal and output an output voltage signal; a transformer configured to receive the output voltage signal and output a load voltage signal to a load; a sensing inductor configured to output a sensed current signal in accordance with a magnetic coupling with the transformer; a digitally controlled phase shifter configured to receive the output voltage signal and output a phase-shifted voltage signal in accordance with a phase control code; a mixer configured to output a mixed current signal in accordance with a mixing of the sensed current signal and the phase-shifted voltage signal; and a transimpedance amplifier with of a low-pass response configured to convert the mixed current signal into a mean voltage signal.

Abstract: A RF (radio frequency) signal detector includes an I/Q (in-phase/quadrature) mixer configured to convert an amplified signal, received from a low-noise amplifier, into a baseband signal having an in-phase component and a quadrature component in accordance with a LO (local oscillator) signal; a local oscillator configured to output the LO signal; a pair of baseband filters configured to output a filtered signal comprising an in-phase component and a quadrature component; a pair of 3-level slicers configured to receive the filtered signal and output a sliced signal having an in-phase component and a quadrature component; a pair of data flip flops configured to sample the sliced signal into a decision including an in-phase component and a quadrature component in accordance with a sampling clock signal; and a digital signal processor configured to determine an existence and characteristic of a component of the RF signal around a frequency of the LO signal.

Abstract: Embodiments described herein provide circuitry employing one or more inductors having an unconventional turn-ratio. The circuitry includes a primary inductor having a first length located on a first layer of an integrated circuit (IC). The circuitry further includes a secondary inductor having a second length located on a second layer of the IC different from the first layer, whereby the second length is greater than the first length, with a ratio between the first and the second lengths corresponding to a non-integer turn-ratio.

Abstract: An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.

Abstract: An apparatus includes a first common-source amplifier having a first PMOS (p-channel metal oxide semiconductor) transistor configured to receive a first voltage and output a first current; a second common-source amplifier having a first NMOS (n-channel metal oxide semiconductor) transistor configured to receive a second voltage and output a second current, wherein the first common-source amplifier and the second common-source amplifier share a common source node, and an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage; a first common-gate amplifier having a second PMOS transistor configured to receive the first current and output a third current; a second common-gate amplifier having a second NMOS transistor configured to receive the second current and output a fourth current; and a load configured to terminate the third current and the fourth current.

Abstract: An frequency down-converter includes a mixer configured to receive a RF (radio frequency) signal having a first end and a second end and output an intermediate signal comprising a first end and a second end in accordance with a LO (local oscillator) signal having a first end and a second end, wherein the first end and the second end of the LO signal jointly form a two-phase periodic signal of a fundamental frequency approximately equal to a mean frequency of a desired component of the RF signal.

Abstract: An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

Abstract: An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

Abstract: An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.

Abstract: An inductor includes: a first coil of metal trace laid out to be symmetrical with respect to a first axis; a second coil of metal trace laid out to be substantially a mirror image of the first coil of metal trace with respect to a second axis; a first coupling capacitor configured to provide a capacitive coupling between a first segment within the first coil of metal trace and a counterpart of the first segment within the second coil of metal trace; and a second coupling capacitor configured to provide a capacitive coupling between a second segment within the first coil of metal trace and a counterpart of the second segment within the second coil of metal trace.

Abstract: An inductor includes: a first coil of metal trace laid out to be symmetrical with respect to a first axis; a second coil of metal trace laid out to be substantially a mirror image of the first coil of metal trace with respect to a second axis; a first coupling capacitor configured to provide a capacitive coupling between a first segment within the first coil of metal trace and a counterpart of the first segment within the second coil of metal trace; and a second coupling capacitor configured to provide a capacitive coupling between a second segment within the first coil of metal trace and a counterpart of the second segment within the second coil of metal trace.

Abstract: An apparatus having a first coupling network configured to receive an input voltage and output a first gate voltage and a second gate voltage at a first gate node and a second gate node, respectively; a stacked complementary common-source amplifier pair including a first common-source amplifier and a second common-source amplifier configured to receive the first gate voltage and the second gate voltage and output a first drain voltage and a second drain voltage at a first drain node and a second drain node, respectively; a second coupling network configured to provide a coupling between the first drain node and the second drain node to equalize the first drain voltage and the second drain voltage. A first inductor and second inductor couple the first and second drain nodes to a first and second DC node, respectively. Third and fourth inductors are coupled to the first and second inductor.

Abstract: A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.

Abstract: In some implementations, a system includes a voltage regulating circuit and a compensation circuit. The voltage regulating circuit includes a pass element configured to provide a regulated voltage to a load. The compensation circuit is configured to adjust a variable resistance based on a current of the load, the variable resistance being coupled to a gate terminal of the pass element through a capacitor.