Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Abstract: A wafer inspection system includes probe and supporting devices opposite to each other. The probe device includes a probe and an electrically conductive module for transmitting test signal of a driver IC. The supporting device includes a chuck, an annular elastic module detachably disposed on the chuck, and a carrier. The chuck has a supporting portion located correspondingly to a hollow portion of the annular elastic module, which is larger than or equal to the carrier in size on an imaginary horizontal plane, enabling the carrier carrying a wafer to be placed on the supporting portion to be electrically connected with the annular elastic module. When the wafer is contacted by the probe, the electrically conductive module is abutted against the annular elastic module to form a short-path test loop. As a result, it is convenient to pick and place the carrier and wafer, enhancing inspection efficiency.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Abstract: Methods and computer-implemented methods are used to predict a risk of cardiovascular disease by using a machine learning mode to analyze a relationship between the occurrence of cardiovascular disease and the health data of patients.

Abstract: A data processing device includes a base plate and an electronic module. The base plate includes N driving portions. The electronic module includes an electronic component, a tray and a recognition mechanism. The tray is configured to support the electronic component and includes N slots. The tray is disposed on the base plate, such that an i-th driving portion of the N driving portions is disposed in an i-th slot of the N slots. The recognition mechanism is disposed on the tray. The recognition mechanism includes N interfering portions and N receiving recesses. When the tray moves with respect to the base plate toward a first direction, the i-th driving portion moves within the i-th slot toward a second direction to push an i-th interfering portion of the N interfering portions to move, such that the i-th interfering portion extends into an i-th receiving recess of the N receiving recesses.

Abstract: A server includes a relay unit adapted to transmit a video data related to a livestream from a terminal of a livestreamer of the livestream to a terminal of a viewer, a determination unit adapted to determine whether the livestream has been terminated for an unexpected reason, a maintaining unit adapted to maintain a state of the livestream when it is determined that the livestream has been terminated, and a resume unit adapted to resume the livestream with the maintained state when the resume unit receives an instruction to resume the livestream from the terminal of the livestreamer within a predetermined period after it is determined that the livestream has been terminated.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: A device with lock function includes a housing, a casing and a lock mechanism. The housing has a first engaging portion. The lock mechanism includes a frame, a lock member, a first elastic member, an operating member and an unlock member. The frame has a second engaging portion. The lock member has a third engaging portion engaging with the first engaging portion to lock the casing in the housing. The unlock member has a fourth engaging portion engaging with the second engaging portion to restrain the operating member. When the unlock member is pressed, the fourth engaging portion disengages from the second engaging portion and the first elastic member drives the lock member to move toward an inside of the frame, such that the third engaging portion disengages from the first engaging portion and the lock member drives the operating member to move toward an outside of the frame.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor and a controller. The battery module is configured to supply power to the electronic device. The processor has a power consumption limit. In a power connection state, the controller determines whether to disable a power consumption limit adjustment function of the processor according to a source power provided by a power adapter and a system performance use setting of the electronic device. When the power consumption limit adjustment function is disabled, the processor executes an application program to monitor a storage capacity of the battery module and adjusts the system performance usage setting according to the storage capacity.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.