Patents by Inventor Po-Han CHENG

Po-Han CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12249493
    Abstract: A method includes loading a wafer over a wafer chuck in a process chamber; performing a deposition process on the loaded wafer; supplying a fluid medium to a fluid guiding structure in the wafer chuck from a fluid inlet port on the wafer chuck, the fluid guiding structure comprising a plurality of arc-shaped channels fluidly communicated with each other; guiding the fluid medium from a first one of the arc-shaped channels of the fluid guiding structure to a second one of the arc-shaped channels of the fluid guiding structure. The second one of the arc-shaped channels of the fluid guiding structure is concentric with the first one of the arc-shaped channels of the fluid guiding structure from a top view.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun Yang, Yi-Ming Lin, Po-Wei Liang, Chu-Han Hsieh, Chih-Lung Cheng, Po-Chih Huang
  • Patent number: 12243837
    Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
  • Publication number: 20250057991
    Abstract: A nanomaterial composition for magnetic field-induced electrical stimulation of cells includes a piezoelectric nanoparticle and a magnetic nanodisc. The piezoelectric nanoparticle is conjugated to a first molecule of a specific binding molecule pair and is coated with a cell-binding molecule. The magnetic nanodisc is conjugated to a second molecule of the specific binding molecule pair and is attached to the piezoelectric nanoparticle through bonding of the second molecule and the first molecule. The magnetic nanodisc converts a magnetic energy into a mechanical energy in the presence of an external magnetic field, and the mechanical energy is then applied to the piezoelectric nanoparticle that is in contact with the cells via the cell-binding molecule, such that the piezoelectric nanoparticle converts the mechanical energy into an electrical energy, so as to electrically stimulate the cells. A method for magnetic field-induced electrical stimulation of cells in a subject is also provided.
    Type: Application
    Filed: December 14, 2023
    Publication date: February 20, 2025
    Inventors: Po-Han Chiang, Chao-Chun Cheng
  • Patent number: 12093111
    Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: September 17, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Po-Han Cheng, Chin-Chang Chang, Po-Hsin Chang, Shih-Hao Chen, Kai-Peng Chung, Ci-Syuan Wu, Chun Tsao, Teng-Chih Wang, Sheng-Yi Chen, Guan-Heng Lai
  • Publication number: 20240272696
    Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor and a controller. The battery module is configured to supply power to the electronic device. The processor has a power consumption limit. In a power connection state, the controller determines whether to disable a power consumption limit adjustment function of the processor according to a source power provided by a power adapter and a system performance use setting of the electronic device. When the power consumption limit adjustment function is disabled, the processor executes an application program to monitor a storage capacity of the battery module and adjusts the system performance usage setting according to the storage capacity.
    Type: Application
    Filed: November 14, 2023
    Publication date: August 15, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Kuo Ko, Po-Han Cheng, Po-Hsin Chang, Huei-Ling Lai
  • Publication number: 20230266813
    Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.
    Type: Application
    Filed: October 14, 2022
    Publication date: August 24, 2023
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Po-Han Cheng, Chin-Chang Chang, Po-Hsin Chang, Shih-Hao Chen, Kai-Peng Chung, Ci-Syuan Wu, Chun Tsao, Teng-Chih Wang, Sheng-Yi Chen, Guan-Heng Lai
  • Patent number: 10305027
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 28, 2019
    Assignees: Kabushiki Kaisha Toshiba, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yushi Kato, Tadaomi Daibou, Yuuzo Kamiguchi, Naoharu Shimomura, Junichi Ito, Hiroaki Sukegawa, Mohamed Belmoubarik, Po-Han Cheng, Seiji Mitani, Tadakatsu Ohkubo, Kazuhiro Hono
  • Publication number: 20180090671
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 29, 2018
    Applicants: Kabushiki Kaisha Toshiba, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yushi KATO, Tadaomi DAIBOU, Yuuzo KAMIGUCHI, Naoharu SHIMOMURA, Junichi ITO, Hiroaki SUKEGAWA, Mohamed BELMOUBARIK, Po-Han CHENG, Seiji MITANI, Tadakatsu OHKUBO, Kazuhiro HONO