Patents by Inventor POHAN KUNG

POHAN KUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961891
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Publication number: 20230387230
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Publication number: 20220216317
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Patent number: 11282934
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Patent number: 11271103
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pohan Kung, Ying-Jing Lu, Chi-Cheng Hung, Yu-Sheng Wang, Shiu-Ko Jangjian
  • Publication number: 20210028290
    Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
    Type: Application
    Filed: November 22, 2019
    Publication date: January 28, 2021
    Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
  • Publication number: 20210005743
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: POHAN KUNG, YING -JING LU, CHI-CHENG HUNG, YU-SHENG WANG, SHIU-KO JANGJIAN
  • Patent number: 10515807
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Fen Chien, Chih-Hsiang Fan, Hsiao-Kuan Wei, Pohan Kung, Hsien-Ming Lee
  • Publication number: 20190385855
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Fen CHIEN, Chih-Hsiang FAN, Hsiao-Kuan WEI, Pohan KUNG, Hsien-Ming LEE
  • Publication number: 20160276156
    Abstract: A semiconductor device is provided which includes a dielectric layer over a gate structure of the semiconductor device. The semiconductor device also includes a conductive interconnect configured to couple the gate structure with an I/O region over the conductive interconnect. The semiconductor also includes a metal silicide layer disposed between the conductive interconnect and the dielectric layer where the metal silicide is a silicide form of a metal different from the conductive interconnect.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: POHAN KUNG, YING -JING LU, CHI-CHENG HUNG, YU-SHENG WANG, SHIU-KO JANGJIAN