Patents by Inventor Po-Hao WANG

Po-Hao WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126174
    Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Che Tu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20240121523
    Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Kai-Hao CHANG, Chun-Yuan WANG, Shin-Hong KUO, Zong-Ru TU, Po-Hsiang WANG, Chih-Ming WANG
  • Patent number: 11951637
    Abstract: A calibration apparatus includes a processor, an alignment device, and an arm. The alignment device captures images in a three-dimensional space, and a tool is arranged on a flange of the arm. The processor records a first matrix of transformation between an end-effector coordinate-system and a robot coordinate-system, and performs a tool calibration procedure according to the images captured by the alignment device for obtaining a second matrix of transformation between a tool coordinate-system and the end-effector coordinate-system. The processor calculates relative position of a tool center point of the tool in the robot coordinate-system based on the first and second matrixes, and controls the TCP to move in the three-dimensional space for performing a positioning procedure so as to regard points in an alignment device coordinate-system as points of the TCP, and calculates the relative positions of points in the alignment device coordinate-system and in the robot coordinate-system.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: April 9, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Hao Huang, Shi-Yu Wang, Po-Chiao Huang, Han-Ching Lin, Meng-Zong Li
  • Patent number: 11955423
    Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
  • Publication number: 20240113089
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tian Hu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11942417
    Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chi Chu, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11879129
    Abstract: This disclosure concerns the use of endogenous plant RNAi machinery to preferentially or specifically reduce transgene expression. In some embodiments, the disclosure concerns specific reduction of transgene expression in seed tissues of a dicot plant.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: January 23, 2024
    Inventors: Andrew J. Bowling, Marcelo Ariel German, Todd P. Glancy, Sandeep Kumar, Heather Pence, Andrew E. Robinson, Shreedharan Sriram, Po-Hao Wang, Carla N. Yerkes
  • Patent number: 11869100
    Abstract: The embodiments of the present application provide a data consolidation analysis method and a data consolidation analysis method. The data consolidation analysis system includes: a first acquiring module, which is configured to acquire machine event data; a second acquiring module, which is configured to acquire production event data; a data processing module, which is connected with the first acquiring module and the second acquiring module and configured to acquire a raw process time of each product and a production capacity index of each batch of products; and an analyzing module, which is connected with the data processing module and configured to acquire a first matching relationship between the production capacity index of each batch of products and the raw process time of each product.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Po-Hao Wang
  • Publication number: 20230281220
    Abstract: A method and device for data synchronization, a storage medium and an electronic device are provided. The method for data synchronization includes operations as follows. Synchronization configuration information for data to be synchronized is determined, and the synchronization configuration information at least includes a data identification of the data to be synchronized and a source data table identification of a source data table where the data to be synchronized is located. A source database is queried based on the source data table identification to obtain a target source data table where the data to be synchronized is located. A field identification of the data to be synchronized is determined from the target source data table based on the data identification. A target data table is constructed based on the field identification, and the data to be synchronized is synchronized into the target data table.
    Type: Application
    Filed: August 30, 2022
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: CHUNG-HSIUNG LEE, Kewu Sun, Lu Yu, Po-Hao Wang, Delong Huang
  • Publication number: 20230203528
    Abstract: Embodiments disclosed herein relate to the field of plant molecular biology, specifically to DNA constructs for conferring insect resistance to a plant. Embodiments disclosed herein relate to insect resistant corn plant containing event DAS-01131-3, and to assays for detecting the presence of event DAS-01131-3 in samples and compositions thereof.
    Type: Application
    Filed: November 15, 2022
    Publication date: June 29, 2023
    Applicant: PIONEER HI-BRED INTERNATIONAL, INC.
    Inventors: ANDREW ASBERRY, BIN CONG, VIRGINIA CRANE, JAMES EDWARD KING, JASDEEP S. MUTTI, DENNIS O'NEILL, M. ALEJANDRA PASCUAL, MARIA MAGDALENA VAN DYK, PO-HAO WANG, AARON T. WOOSLEY, SARAH E. WORDEN
  • Publication number: 20230136893
    Abstract: This disclosure concerns the use of endogenous plant RNAi machinery to preferentially or specifically reduce transgene expression. In some embodiments, the disclosure concerns specific reduction of transgene expression in seed tissues of a dicot plant.
    Type: Application
    Filed: September 12, 2022
    Publication date: May 4, 2023
    Applicant: CORTEVA AGRISCIENCE LLC
    Inventors: ANDREW J. BOWLING, MARCELO ARIEL GERMAN, TODD P. GLANCY, SANDEEP KUMAR, HEATHER PENCE, ANDREW E. ROBINSON, SHREEDHARAN SRIRAM, PO-HAO WANG, CARLA N. YERKES
  • Patent number: 11527491
    Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 13, 2022
    Assignee: Siliconware Precision Industries Co., Ltd
    Inventors: Po-Hao Wang, Chun-Tang Lin, Shou-Qi Chang, Yu-Hsiang Hsieh
  • Patent number: 11473095
    Abstract: This disclosure concerns the use of endogenous plant RNAi machinery to preferentially or specifically reduce transgene expression. In some embodiments, the disclosure concerns specific reduction of transgene expression in seed tissues of a dicot plant.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: October 18, 2022
    Assignee: CORTEVA AGRISCIENCE LLC
    Inventors: Sandeep Kumar, Marcelo Ariel German, Po-Hao Wang, Todd P. Glancy, Shreedharan Sriram, Carla N. Yerkes, Andrew J. Bowling, Heather Pence, Andrew E. Robinson
  • Publication number: 20220092706
    Abstract: The embodiments of the present application provide a data consolidation analysis method and a data consolidation analysis method. The data consolidation analysis system includes: a first acquiring module, which is configured to acquire machine event data; a second acquiring module, which is configured to acquire production event data; a data processing module, which is connected with the first acquiring module and the second acquiring module and configured to acquire a raw process time of each product and a production capacity index of each batch of products; and an analyzing module, which is connected with the data processing module and configured to acquire a first matching relationship between the production capacity index of each batch of products and the raw process time of each product.
    Type: Application
    Filed: October 28, 2021
    Publication date: March 24, 2022
    Inventor: Po-Hao WANG
  • Patent number: 11227842
    Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 18, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chang-Fu Lin, Chun-Tang Lin, Bo-Hao Chang
  • Publication number: 20210296261
    Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Po-Hao Wang, Chun-Tang Lin, Shou-Qi Chang, Yu-Hsiang Hsieh
  • Patent number: 11056442
    Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 6, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chun-Tang Lin, Shou-Qi Chang, Yu-Hsiang Hsieh
  • Publication number: 20200350261
    Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 5, 2020
    Inventors: Po-Hao Wang, Chang-Fu Lin, Chun-Tang Lin, Bo-Hao Chang
  • Patent number: 10763223
    Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 1, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chang-Fu Lin, Chun-Tang Lin, Bo-Hao Chang
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin