Abstract: A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: The present disclosure discloses an image processing circuit having output timing adjustment mechanism. An image enhancement circuit performs image enhancement on an input image to generate an enhanced image. A first image processing path and a second image processing path respectively perform processing on the enhanced image having a first timing and the enhanced image having a second timing to generate a first output image and a second output image. A timing control circuit adjusts the timing of the enhanced image according to requirements of the first image processing path and the second image processing path to generate the enhanced image having the first timing and the enhanced image having the second timing. A first image output interface outputs the first output image. A second image output interface outputs the second output image.

Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.

Abstract: An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.

Abstract: A display includes a system on chip (SoC), a plurality of driver integrated circuits (ICs), and a plurality of groups of light-emitting diodes (LEDs). The SoC is arranged to generate a plurality of backlight control signals according to an input image data. The plurality of driver ICs are coupled to the SoC, and arranged to receive the plurality of backlight control signals, respectively, to generate a plurality of driving signals. The plurality of groups of LEDs are coupled to the plurality of driver ICs, respectively, wherein the plurality of driving signals are arranged to control brightness of the plurality of groups of LEDs, respectively.

Abstract: A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Abstract: A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.

Abstract: A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Abstract: A signal processing method for maintaining a signal relative relationship and an electronic device thereof are provided. The signal processing method includes: detecting that a current input period of a vertical synchronization signal changes relative to a previous input period; determining whether a frequency difference between a pulse width modulation signal and the vertical synchronization signal is within an acceptable range, and when the frequency difference is not within the acceptable range, performing a frequency adjustment stage to adjust a period of the pulse width modulation signal to be close to the current input period; selectively performing a phase adjustment stage to adjust a phase of the pulse width modulation signal to a phase of the vertical synchronization signal; and maintaining a relative phase relationship between the pulse width modulation signal and the vertical synchronization signal.

Abstract: A video processing method for a video processing circuit includes receiving a first video source corresponding to a first pixel rate and a second video source corresponding to a second pixel rate, wherein a processing data rate of a video processing path is greater than or equal to a sum of the first pixel rate and the second pixel rate. The method further includes using the processing data rate to sequentially perform an image processing to a first image of the first video source and a second image of the second video source corresponding to the same display time, to generate a first processed image and a second processed image.

Abstract: A signal processing method for maintaining a signal relative relationship and an electronic device thereof are provided. The signal processing method includes: detecting that a current input period of a vertical synchronization signal changes relative to a previous input period; determining whether a frequency difference between a pulse width modulation signal and the vertical synchronization signal is within an acceptable range, and when the frequency difference is not within the acceptable range, performing a frequency adjustment stage to adjust a period of the pulse width modulation signal to be close to the current input period; selectively performing a phase adjustment stage to adjust a phase of the pulse width modulation signal to a phase of the vertical synchronization signal; and maintaining a relative phase relationship between the pulse width modulation signal and the vertical synchronization signal.

Abstract: A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.

Abstract: The present invention discloses an image processing circuit including an image processing unit, a frame rate adjusting circuit and a phase detection and control circuit. In operations of the image processing circuit, the image processing unit is configured to process an input image signal including a plurality of frames to generate a processed image signal including a plurality of processed frames, the frame rate adjusting circuit is configured to adjust a row number of vertical blanking intervals of at least one of the processed frames according to a control signal, to generate an output image signal including at least one adjusted frame, and the phase detection and control circuit is configured to determine a phase relationship of the input image signal or the processed image signal and the output image signal to generate the control signal.

Abstract: A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.

Abstract: A video processing method for a video processing circuit includes receiving a first video source corresponding to a first pixel rate and a second video source corresponding to a second pixel rate, wherein a processing data rate of a video processing path is greater than or equal to a sum of the first pixel rate and the second pixel rate, and using the processing data rate to sequentially perform an image processing to a first image of the first video source and a second image of the second video source corresponding to the same display time, to generate a first processed image and a second processed image.

Abstract: A clock switching apparatus is provided. The clock input terminal receives a first clock signal as an input clock signal at first and start to receive a second clock signal as the input clock signal during a masking state of a masking signal within a clock-switching time period. The enabling synchronizing circuit receives a clock-switching enabling signal, receives the input clock signal and generate a synchronized enabling signal accordingly. The masking circuit receives the synchronized enabling signal and the mask signal to generate a final enabling signal. The output circuit receives the input clock signal, receive the final enabling signal that disables the output circuit only when either the masking signal is at the masking state or the synchronized enabling signal is at the clock-switching enabling state, and generate an output clock signal according to the input clock signal when the output circuit is enabled.

Abstract: The disclosure provides a brake and shift control assembly configured to be mounted on a bicycle head. The brake and shift control assembly includes a brake module and a shift control module. The brake module is mounted on one of the holding parts. The shift control module includes a signal generator, a fixing assembly, a circuit board, a wire, a battery and an antenna. The signal generator is disposed on the brake module. The fixing assembly is disposed on bicycle head. The circuit board is disposed in the fixing assembly and electrically connected to the signal generator via the wire. The battery and the antenna are disposed on the circuit board.