Patents by Inventor Po-Kuan HO

Po-Kuan HO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing an interconnection structure having a bottom via spacer
    Patent number: 11984355
    Abstract: A method includes providing a semiconductor structure including a dielectric layer having an opening exposing a top surface of a metal layer. A bottom via is selectively deposited in the opening and over the metal layer. A barrier layer is deposited over the bottom via and in contact with the dielectric layer at a sidewall of the opening. A top via is formed in the opening, in contact with the barrier layer, and over the bottom via. The top via is separated from the dielectric layer by the barrier layer.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kuan Ho, Chia-Tien Wu
  • Method for manufacturing an interconnect structure having a selectively formed bottom via
    Patent number: 11488861
    Abstract: A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the first dielectric layer. An opening is formed in the second dielectric layer to expose the conductive element. A dielectric spacer layer is selectively formed to be in contact with surfaces defining the opening of the second dielectric layer. The dielectric spacer layer exposes the conductive element. A bottom via is formed in the opening and in contact with the dielectric spacer layer and the conductive element. A portion of the dielectric spacer layer is removed to form a dielectric spacer in contact with the bottom via. A top via is formed in the opening and over the bottom via and the dielectric spacer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Kuan Ho, Chia-Tien Wu
  • METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE
    Publication number: 20220293465
    Abstract: A method includes providing a semiconductor structure including a dielectric layer having an opening exposing a top surface of a metal layer. A bottom via is selectively deposited in the opening and over the metal layer. A barrier layer is deposited over the bottom via and in contact with the dielectric layer at a sidewall of the opening. A top via is formed in the opening, in contact with the barrier layer, and over the bottom via. The top via is separated from the dielectric layer by the barrier layer.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kuan HO, Chia-Tien WU
  • METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE
    Publication number: 20210013096
    Abstract: A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the first dielectric layer. An opening is formed in the second dielectric layer to expose the conductive element. A dielectric spacer layer is selectively formed to be in contact with surfaces defining the opening of the second dielectric layer. The dielectric spacer layer exposes the conductive element. A bottom via is formed in the opening and in contact with the dielectric spacer layer and the conductive element. A portion of the dielectric spacer layer is removed to form a dielectric spacer in contact with the bottom via. A top via is formed in the opening and over the bottom via and the dielectric spacer.
    Type: Application
    Filed: September 11, 2020
    Publication date: January 14, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kuan HO, Chia-Tien WU
  • Interconnection structure having top and bottom vias with a barrier layer therebetween and a dielectric spacer at the bottom via
    Patent number: 10777452
    Abstract: An interconnection structure includes a first dielectric layer, a conductive element, a second dielectric layer, a bottom via, a dielectric spacer, and a top via. The conductive element is embedded in the first dielectric layer. The second dielectric layer is over the first dielectric layer and the conductive element. The second dielectric layer has an opening exposing the conductive element. The bottom via is disposed in the opening and in contact with the conductive element. The dielectric spacer is disposed in the opening and is in contact with the bottom via and the second dielectric layer. The top via is disposed in the opening and covering the bottom via and the dielectric spacer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Kuan Ho, Chia-Tien Wu
  • Interconnection Structure and Manufacturing Method Thereof
    Publication number: 20190080960
    Abstract: An interconnection structure includes a first dielectric layer, a conductive element, a second dielectric layer, a bottom via, a dielectric spacer, and a top via. The conductive element is embedded in the first dielectric layer. The second dielectric layer is over the first dielectric layer and the conductive element. The second dielectric layer has an opening exposing the conductive element. The bottom via is disposed in the opening and in contact with the conductive element. The dielectric spacer is disposed in the opening and is in contact with the bottom via and the second dielectric layer. The top via is disposed in the opening and covering the bottom via and the dielectric spacer.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Po-Kuan HO, Chia-Tien WU