Abstract: Embodiments relate to a neural processor circuit that includes a first number of neural engine circuits, a second number of channels and a data processor circuit. The first number of neural engine circuits are pipelined into the second number of chains smaller than the first number. Each of the chains is configured to generate output data of a first size. Each of the channels is coupled to each of the chains and configured to transmit the output data from each of the neural engine circuits in the chains sequentially. The data processor circuit is coupled to the channels to receive the output data. The data processor circuit aggregates the output data of each of the chains into aggregated data of a second size larger than the first size and writes the aggregated data of the second size into a buffer memory of the data processor circuit.

Abstract: Embodiments relate to a neural processor circuit including one or more planar engine circuits that perform non-convolution operations in parallel with convolution operations performed by one or more neural engine circuits. The neural engine circuits perform the convolution operations on neural input data corresponding to one or more neural engine tasks to generate neural output data. The planar engine circuits perform non-convolution operations on planar input data corresponding to one or more planar engine tasks to generate planar output data. A data processor circuit that includes multiple buffer circuits performs task skew management between the one or more neural engine tasks and the one or more planar engine tasks. The data processor circuit stops addition of an incoming task to queues in response to one or more of the queues stored in the buffer circuits reaching a threshold.

Abstract: Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.

Abstract: Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.

Abstract: Systems and methods for improving operation of a video encoding pipeline, which includes a sample adaptive offset block that selects an offset sample from image data corresponding with a coding unit; determines edge offset parameters including a first mapping of an edge classification to an edge offset value and band offset parameters including a second mapping of a band classification to a band offset value based at least in part on analysis of the offset sample; and determines sample adaptive offset parameters based at least in part on a first rate-distortion cost associated with the edge offset parameters and a second rate-distortion cost associated with the band offset parameters. Additionally, a decoding device may apply offsets to decoded image data corresponding with the coding unit based at least in part on the sample adaptive offset parameters.

Abstract: Systems and methods for improving operation of a video encoding pipeline, which includes a sample adaptive offset block that selects an offset sample from image data corresponding with a coding unit; determines edge offset parameters including a first mapping of an edge classification to an edge offset value and band offset parameters including a second mapping of a band classification to a band offset value based at least in part on analysis of the offset sample; and determines sample adaptive offset parameters based at least in part on a first rate-distortion cost associated with the edge offset parameters and a second rate-distortion cost associated with the band offset parameters. Additionally, a decoding device may apply offsets to decoded image data corresponding with the coding unit based at least in part on the sample adaptive offset parameters.