Abstract: The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.

Abstract: Acceleration-ready program development includes providing a software library having a plurality of functions having compute identifiers. The software library is associated with a hardware library including one or more hardware accelerated functions. The hardware accelerated functions are associated with the compute identifiers. Each hardware accelerated function is a functional equivalent of a function of the software library having the same compute identifier. A hybrid executor layer is provided that, when executed by a data processing system with an acceleration-ready computer program built using the software library, is configured to initiate execution of a selected function of the acceleration-ready computer program using a processor of the data processing system or invoke a hardware accelerated function having a compute identifier matching the compute identifier of the selected function based on comparing acceleration criteria with acceleration rules.

Abstract: An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.

Abstract: An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.

Abstract: In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.

Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

Abstract: Apparatus and method relate to a data channel. In this apparatus, an input circuit is configured to gate a valid input with a ready output to provide a forward token (“f-token”) to a first f-token register of a f-token pipeline and to a counter, and to receive data to a first data register of a data pipeline. An output circuit is configured to gate a ready input with a valid output to provide a return token (“r-token”) to a first r-token register of a r-token pipeline and to a FWFT FIFO, to receive the f-token from a second f-token register of the f-token pipeline to the FWFT FIFO, and to receive the data from a second data register of the data pipeline to the FWFT FIFO. The input circuit receives the r-token from the first r-token register to a second r-token register of the r-token pipeline for the counter.

Abstract: An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Abstract: An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Abstract: In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit includes at least one multiplexer each coupled to receive as input a true version and a complement version of a bit of the W-bit key. Each of the at least one multiplexer is controlled by a respective pair of memory outputs of the plurality of memory outputs. The at least one compare circuit further includes combinatorial logic coupled to perform at least one logical AND operation based on output of the at least one multiplexer.

Abstract: In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit includes at least one multiplexer each coupled to receive as input a true version and a complement version of a bit of the W-bit key. Each of the at least one multiplexer is controlled by a respective pair of memory outputs of the plurality of memory outputs. The at least one compare circuit further includes combinatorial logic coupled to perform at least one logical AND operation based on output of the at least one multiplexer.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.