Patents by Inventor Ponnamanda Venkata Chandra Sekhar

Ponnamanda Venkata Chandra Sekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11108364
    Abstract: A circuit for signal classification in a digital pre-distortion (DPD) system is provided. The circuit includes a first frequency path with a positive frequency translation to generate a first power level corresponding to a signal output of the first frequency path, a second frequency path with a negative frequency translation to generate a second power level corresponding to a signal output of the second frequency path, and a third frequency path configured to filter the input signal via a high pass filter (HPF) and to generate a third power level corresponding to a signal output of the third frequency path. The circuit further includes a processing unit configured to compute frequency content metrics corresponding to the input signal based on the first power level, the second power level and the third power level for selecting a set of DPD coefficients for the DPD circuit.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: August 31, 2021
    Assignee: Xilinx, Inc.
    Inventors: Vincent C Barnes, Ponnamanda Venkata Chandra Sekhar, Prateek Jha
  • Patent number: 7593459
    Abstract: A wireless link simulator includes, in sequence, a digital transmit device under test (TX-DUT), a wireless link simulator, and a digital receive device under test (RX-DUT). The wireless link simulator includes, in sequence, a transmitter IQ imbalance generator, a power amplifier non-linearity generator, a noise floor generator, a multi-path channel generator, a receive noise generator, a frequency offset generator, a phase noise generator, a receive IQ imbalance generator, and a DC offset generator. Each of the generators may be individually varied to determine the receiver sensitivity to each of these effects and associated parameters.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: September 22, 2009
    Assignee: Redpine Signals, Inc.
    Inventors: Narasimhan Venkatesh, Ravikumar Neerudu, Ponnamanda Venkata Chandra Sekhar
  • Patent number: 7298772
    Abstract: A integrated system for generation of packet detection, symbol timing, and coarse frequency offset for an orthogonal frequency division multiplexed (OFDM) receiver having a stream of input symbols applied comprises a first multiplier performing a multiplication on a delayed and conjugated stream of input symbols multiplied by the input symbol stream. The output of the first multiplier is summed over a symbol length. A second multiplier has an output formed from multiplying the delayed symbol stream by its conjugate, thereby providing a signal strength term Pn. The output of the second multiplier is summed over two symbol periods, and multiplied by a known threshold to form a threshold value. When the magnitude of cn term rises above the known threshold, this generates a packet detect output, and when the magnitude of Cn terms thereafter falls below the known threshold, this generates a symbol timing output.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: November 20, 2007
    Assignee: Redpine Signals, Inc.
    Inventors: Ravikumar Neerudu, Narasimhan Venkatesh, Ponnamanda Venkata Chandra Sekhar