Patents by Inventor Ponnarith Pok

Ponnarith Pok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for low clamping voltage ESD solution for transient sensitive applications
    Patent number: 10714933
    Abstract: An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ponnarith Pok, Timothy Don Davis
  • Method and Apparatus for Low Clamping Voltage ESD Solution for Transient Sensitive Applications
    Publication number: 20170373494
    Abstract: An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Ponnarith Pok, Timothy Don Davis
  • ESD protection using diode-isolated gate-grounded nMOS with diode string
    Patent number: 9269703
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 23, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
  • ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE STRING
    Publication number: 20140342515
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 20, 2014
    Inventors: Ponnarith POK, Kyle SCHULMEYER, Roger A. CLINE, Charvaka DUVVURY
  • ESD protection using diode-isolated gate-grounded NMOS with diode string
    Patent number: 8829618
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
  • ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE STRING
    Publication number: 20120112286
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 10, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury