Abstract: A video decoding apparatus for decoding an encoded video bitstream having frames of video data encoded in rows of macroblocks. The video decoding apparatus comprises a parsing unit configured to receive the encoded video bitstream and to interpret the encoded video bitstream to generate items of macroblock information to be used for reconstructing the video frames of video data. The parsing unit is configured to store the items of macroblock information in a memory in bitstream order. The video decoding apparatus further comprises a line control unit configured to generate line control information associated with each row of macroblocks, the line control information comprising a sequence of pointers to the items of macroblock information stored in the memory, such that sequentially reading the sequence of pointers accesses the items of macroblock information in raster scan order. The line control information is stored in said memory in association with said items of macroblock information.

Abstract: A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.

Abstract: A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.

Abstract: A video decoding apparatus for decoding an encoded video bitstream having frames of video data encoded in rows of macroblocks. The video decoding apparatus comprises a parsing unit configured to receive the encoded video bitstream and to interpret the encoded video bitstream to generate items of macroblock information to be used for reconstructing the video frames of video data. The parsing unit is configured to store the items of macroblock information in a memory in bitstream order. The video decoding apparatus further comprises a line control unit configured to generate line control information associated with each row of macroblocks, the line control information comprising a sequence of pointers to the items of macroblock information stored in the memory, such that sequentially reading the sequence of pointers accesses the items of macroblock information in raster scan order. The line control information is stored in said memory in association with said items of macroblock information.

Abstract: A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.

Abstract: A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.

Abstract: A method of generating digital control parameters for implementing digital logic circuitry comprising functional nodes with at least one input or at least one output and connections indicating interconnections between said functional nodes, wherein said digital logic circuitry comprises a first path streamed by successive tokens, and a second path streamed by said tokens is disclosed. The method comprises determining a necessary relative throughput for data flow to said paths; assigning buffers to one of said paths to balance throughput of said paths; removing assigned buffers until said necessary relative throughput is obtained with minimized number of buffers; and generating digital control parameters for implementing said digital logic circuitry comprising said minimized number of buffers. An apparatus, a computer implemented digital logic circuitry, a Data Flow Machine, methods and computer program products are also disclosed.

Abstract: Methods and apparatuses for automatically forming a data flow machine using a graph representing source code are provided. At least one first hardware element may be configured to perform at least one first function associated with a respective node in the graph. A firing rule for at least one of the at least one configured first hardware element may be identified. At least one second hardware element may be configured to perform at least one second function associated with a respective connection between nodes in the graph.