Patents by Inventor Pooja Chilukuri

Pooja Chilukuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solder structures including barrier layers with nickel and/or copper
    Patent number: 7839000
    Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: November 23, 2010
    Assignee: Unitive International Limited
    Inventors: J. Daniel Mis, Gretchen Adema, Susan Bumgarner, Pooja Chilukuri, Christine Rinne, Glenn Rinne
  • Solder Structures Including Barrier Layers with Nickel and/or Copper
    Publication number: 20090212427
    Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.
    Type: Application
    Filed: May 8, 2009
    Publication date: August 27, 2009
    Inventors: J. Daniel Mis, Gretchen Adema, Susan Bumgarner, Pooja Chilukuri, Christine Rinne, Glenn Rinne
  • Methods of forming lead free solder bumps
    Patent number: 7547623
    Abstract: Methods of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate. A nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer. In addition, a solder layer may be formed on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer. In addition, a copper layer may be formed on the under bump seed metallurgy layer before forming the nickel layer with portions of the under bump seed metallurgy layer being free of the copper layer. Accordingly, the under bump seed metallurgy layer may be between the copper layer and the electronic substrate, and the copper layer may be between the under bump seed metallurgy layer and the nickel layer. Related structures are also discussed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: June 16, 2009
    Assignee: Unitive International Limited
    Inventors: J. Daniel Mis, Gretchen Adema, Susan Bumgarner, Pooja Chilukuri, Christine Rinne, Glenn Rinne
  • Methods of forming lead free solder bumps and related structures
    Publication number: 20060030139
    Abstract: Methods of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate. A nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer. In addition, a solder layer may be formed on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer. In addition, a copper layer may be formed on the under bump seed metallurgy layer before forming the nickel layer with portions of the under bump seed metallurgy layer being free of the copper layer. Accordingly, the under bump seed metallurgy layer may be between the copper layer and the electronic substrate, and the copper layer may be between the under bump seed metallurgy layer and the nickel layer. Related structures are also discussed.
    Type: Application
    Filed: June 29, 2005
    Publication date: February 9, 2006
    Inventors: J. Mis, Gretchen Adema, Susan Bumgarner, Pooja Chilukuri, Christine Rinne, Glenn Rinne