Abstract: A solution for managing a circuit design, which enables a cell to be incrementally placed in the circuit design based on a resulting wiring distance is provided. A cell to be placed in the circuit design is obtained along with a corresponding set of nets in the circuit design to which the cell is to be connected. A routing grid, which defines a plurality of tiles in the circuit design for consideration in placing the cell, can be generated based on the set of nets for the cell. A wire distance measure can be calculated for each of the tiles in the routing grid using the set of nets. The wire distance measure is then used to identify a target tile for placing the cell. The target tile can be used to find an exact and/or rough placement for the cell.

Abstract: A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.