Abstract: Systems and methods for modifying campaign dependent geofences by creating marketing campaigns and linking the marketing campaign to a specific geofence. Each campaign-linked geofence may be capable of delivering the campaign messages to geofence participants during the duration of a marketing campaign and the geofence system may subsequently deactivate the geofence automatically after the marketing campaign has concluded. The systems and methods may map a geofence with a defined boundary to specified location on the map coinciding with the marketing campaign. As the tracked computer devices impinges on the borders of the market campaign's geofence, select messages may be received by the tracked computer devices, corresponding specifically to the events, promotions and advertisements of the campaign events during the time frame the events are active.

Abstract: Systems and methods for modifying campaign dependent geofences by creating marketing campaigns and linking the marketing campaign to a specific geofence. Each campaign-linked geofence may be capable of delivering the campaign messages to geofence participants during the duration of a marketing campaign and the geofence system may subsequently deactivate the geofence automatically after the marketing campaign has concluded. The systems and methods may map a geofence with a defined boundary to specified location on the map coinciding with the marketing campaign. As the tracked computer devices impinges on the borders of the market campaign's geofence, select messages may be received by the tracked computer devices, corresponding specifically to the events, promotions and advertisements of the campaign events during the time frame the events are active.

Abstract: Systems and methods for modifying campaign dependent geofences by creating marketing campaigns and linking the marketing campaign to a specific geofence. Each campaign-linked geofence may be capable of delivering the campaign messages to geofence participants during the duration of a marketing campaign and the geofence system may subsequently deactivate the geofence automatically after the marketing campaign has concluded. The systems and methods may map a geofence with a defined boundary to specified location on the map coinciding with the marketing campaign. As the tracked computer devices impinges on the borders of the market campaign's geofence, select messages may be received by the tracked computer devices, corresponding specifically to the events, promotions and advertisements of the campaign events during the time frame the events are active.

Abstract: Systems and methods for virtual reality cognitive messaging are disclosed. In embodiments, a computer-implemented method, comprises: obtaining, by a computing device, a virtual reality space based on a physical venue; creating, by the computing device, an enhanced virtual reality space by inserting one or more colliders into the virtual reality space, wherein the placement of the one or more colliders in the enhanced virtual reality space maps to a placement of one or more beacons in the physical venue; initiating, by the computing device, a virtual tour of the enhanced virtual reality space; sensing, by the computing device, that a virtual user has collided with one of the one or more colliders in the enhanced virtual reality space during the virtual tour; and sending, by the computing device, a request for event information associated with the one or more beacons in the physical venue to a messaging server.

Abstract: Systems and methods for modifying campaign dependent geofences by creating marketing campaigns and linking the marketing campaign to a specific geofence. Each campaign-linked geofence may be capable of delivering the campaign messages to geofence participants during the duration of a marketing campaign and the geofence system may subsequently deactivate the geofence automatically after the marketing campaign has concluded. The systems and methods may map a geofence with a defined boundary to specified location on the map coinciding with the marketing campaign. As the tracked computer devices impinges on the borders of the market campaign's geofence, select messages may be received by the tracked computer devices, corresponding specifically to the events, promotions and advertisements of the campaign events during the time frame the events are active.

Abstract: Systems and methods for virtual reality cognitive messaging are disclosed. In embodiments, a computer-implemented method, comprises: obtaining, by a computing device, a virtual reality space based on a physical venue; creating, by the computing device, an enhanced virtual reality space by inserting one or more colliders into the virtual reality space, wherein the placement of the one or more colliders in the enhanced virtual reality space maps to a placement of one or more beacons in the physical venue; initiating, by the computing device, a virtual tour of the enhanced virtual reality space; sensing, by the computing device, that a virtual user has collided with one of the one or more colliders in the enhanced virtual reality space during the virtual tour; and sending, by the computing device, a request for event information associated with the one or more beacons in the physical venue to a messaging server.

Abstract: A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.

Abstract: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Abstract: A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.

Abstract: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Abstract: A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.