Patents by Inventor Pooja Roy

Pooja Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10719355
    Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov, Lihu Rappoport, Stanislav Shwartsman, Hong Wang, Adi Yoaz, Ronak Singhal, Robert S. Chappell
  • Patent number: 10496413
    Abstract: A processor includes a memory to hold a buffer to store data dependencies comprising nodes and edges for each of a plurality of micro-operations. The nodes include a first node for dispatch, a second node for execution, and a third node for commit. A detector circuit is to queue, in the buffer, the nodes of a micro-operation; add, to determine a node weight for each of the nodes of the micro-operation, an edge weight to a previous node weight of a connected micro-operation that yields a maximum node weight for the node, wherein the node weight comprises a number of execution cycles of an OOO pipeline of the processor and the edge weight comprises a number of execution cycles to execute the connected micro-operation; and identify, as a critical path, a path through the data dependencies that yields the maximum node weight for the micro-operation.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Jayesh Gaur, Pooja Roy, Sreenivas Subramoney, Hong Wang, Ronak Singhal
  • Publication number: 20190243684
    Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Zeev Sperber, Alexandr Titov, Lihu Rappoport, Stanislav Shwartsman, Hong Wang, Adi Yoaz, Ronak Singhal, Robert S. Chappell
  • Publication number: 20180232235
    Abstract: A processor includes a memory to hold a buffer to store data dependencies comprising nodes and edges for each of a plurality of micro-operations. The nodes include a first node for dispatch, a second node for execution, and a third node for commit. A detector circuit is to queue, in the buffer, the nodes of a micro-operation; add, to determine a node weight for each of the nodes of the micro-operation, an edge weight to a previous node weight of a connected micro-operation that yields a maximum node weight for the node, wherein the node weight comprises a number of execution cycles of an OOO pipeline of the processor and the edge weight comprises a number of execution cycles to execute the connected micro-operation; and identify, as a critical path, a path through the data dependencies that yields the maximum node weight for the micro-operation.
    Type: Application
    Filed: February 15, 2017
    Publication date: August 16, 2018
    Inventors: Jayesh Gaur, Pooja Roy, Sreenivas Subramoney, Hong Wang, Ronak Singhal