Abstract: Various methods and circuital arrangements for controlling an RF amplifier while reducing size, cost and power consumption are presented. Included is an amplifier controller unit that provides different current amplification stages, via corresponding calibration and control blocks, that can be used for calibrating an output power of the RF amplifier based on a reference current. Order of the current amplification stages starting from the reference current allow reduction in size, cost and power consumption. A fixed or programmable offset current may be added to an output current provided by a current amplification stage.

Abstract: Various methods and circuital arrangements for controlling an RF amplifier while reducing size, cost and power consumption are presented. Included is an amplifier controller unit that provides different current amplification stages that can be used for calibrating an output power of the RF amplifier based on a reference current. Order of the current amplification stages starting from the reference current allow reduction in size, cost and power consumption.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: Various methods and circuital arrangements for controlling an RF amplifier while reducing size, cost and power consumption are presented. Included is an amplifier controller unit that provides different current amplification stages, via corresponding calibration and control blocks, that can be used for calibrating an output power of the RF amplifier based on a reference current. Order of the current amplification stages starting from the reference current allow reduction in size, cost and power consumption. A fixed or programmable offset current may be added to an output current provided by a current amplification stage.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Abstract: Various methods and circuital arrangements for controlling an RF amplifier while reducing size, cost and power consumption are presented. Included is an amplifier controller unit that provides different current amplification stages that can be used for calibrating an output power of the RF amplifier based on a reference current. Order of the current amplification stages starting from the reference current allow reduction in size, cost and power consumption.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.

Abstract: The present disclosure provides, in one embodiment, a method of shunting a power supply to reduce output ripple. The method includes determining at least one performance parameter of a DC/DC converter circuit; generating a first reference signal, wherein the first reference signal is based on the performance parameter; comparing the first reference signal to the performance parameter; and generating a shunt current from an input power source to an output node of the DC/DC converter circuit based on, at least in part, the comparison of the performance parameter and the first reference signal.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.

Abstract: The present disclosure provides, in one embodiment, a method of shunting a power supply to reduce output ripple. The method includes determining at least one performance parameter of a DC/DC converter circuit; generating a first reference signal, wherein the first reference signal is based on the performance parameter; comparing the first reference signal to the performance parameter; and generating a shunt current from an input power source to an output node of the DC/DC converter circuit based on, at least in part, the comparison of the performance parameter and the first reference signal.

Abstract: Transmission of a high frequency signal is provided by a passive mixer. The passive mixer receives a low frequency signal as an input. The passive mixer includes a plurality of transistors each with a gate, a source, and a drain. The passive mixer also includes a local oscillator connected to the gates of the transistors. The gates of the transistors are also connected to a DC bias proportional to the threshold voltage of the transistors. In addition, an output of the passive mixer may be attenuated by a passive attenuator wherein both the passive attenuator and passive mixer are substantially free of quiescent current.

Abstract: A method and system of decimating a Pulse Width Modulated (PWM) signal (537) is provided. The method includes computing one or more timestamps (553) of the PWM signal (537), the PWM signal being at a first sample rate (567). The one or more timestamps (553) are computed at a second sample rate (568), which is lower than the first sample rate (567). Thereafter, the method generates a plurality of pre-filter signals (557-n) based on each of the one or more timestamps (553) and a plurality of translation factors (555-n). The plurality of pre-filter signals (557-n) is then filtered at the second sample rate (568) using a plurality of Infinite Impulse Response (IIR) filters (560-n) to generate a plurality of intermediate decimated Pulse Code Modulated (PCM) signals (563). The plurality of intermediate decimated PCM signals (563) is combined to generate a PCM signal (569).

Abstract: An RF modulator supporting wide-band signals includes IQ modulation by interleaving the in-phase and quadrature signals. The modulator can be implemented using an integrated circuit having a baseband in-phase stage that receives an in-phase analog input signal, a baseband quadrature stage that receives a quadrature analog input signal, and a switching mixer having a plurality of switches. The switching mixer receives in-phase and quadrature signals from the baseband in-phase stage and the baseband quadrature stage. The switching mixer produces a differential signal combining the in-phase and quadrature signals by interleaving the signals over a plurality of phases of a carrier period.

Abstract: A method and system of decimating a Pulse Width Modulated (PWM) signal (537) is provided. The method includes computing one or more timestamps (553) of the PWM signal (537), the PWM signal being at a first sample rate (567). The one or more timestamps (553) are computed at a second sample rate (568), which is lower than the first sample rate (567). Thereafter, the method generates a plurality of pre-filter signals (557-n) based on each of the one or more timestamps (553) and a plurality of translation factors (555-n). The plurality of pre-filter signals (557-n) is then filtered at the second sample rate (568) using a plurality of Infinite Impulse Response (IIR) filters (560-n) to generate a plurality of intermediate decimated Pulse Code Modulated (PCM) signals (563). The plurality of intermediate decimated PCM signals (563) is combined to generate a PCM signal (569).

Abstract: A method and system for operating a comparator (602) is provided. The method includes analyzing an output (612) of the comparator (602) based on one or more of a transition of the output, present operational state of the comparator, and at least one time instant corresponding to the output. The method further includes controlling an operational state of the comparator (602) based on the analysis of the output (612).

Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.

Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.