Abstract: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

Abstract: A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.

Abstract: One embodiment of the present invention provides a system that selects instructions to be executed in a computer system that supports out-of-order execution of program instructions. The system receives dependency information for a first instruction. This dependency information identifies preceding instructions in the execution stream of a program that need to complete before the first instruction can be executed. The system divides this dependency information into a recent set and a less recent set. The recent set includes dependency information for a block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed. The less recent set includes dependency information for instructions not in the block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed.

Abstract: According to an embodiment of the present invention, a method and apparatus is described for selecting dependencies between a fast scoreboard and a slow scoreboard in an out of order processor. The processor fetches instructions in groups eight instructions. Each group of eight instructions is mod-eight rotated. The instructions in the scoreboards are configured into multiple octets. A select mask for the first instruction of each octet is generated using a predefined truth table. The select masks for remaining instructions in the octets are generated using the first mask. The write pointer for the current instruction is used to select the masks for the group of eight instructions. The selected masks are then used to multiplex dependencies between the scoreboards. The selected masks are configured to multiplex dependencies between the scoreboards for single or multi-strand operations.