Patents by Inventor Poornima P. Sulibele

Poornima P. Sulibele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687479
    Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Jie Zheng, Deanna Postles Dunn Berger, Chad G. Wilson, Poornima P Sulibele, James Franklin Driftmyer
  • Publication number: 20230085998
    Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Jie Zheng, Deanna Postles Dunn Berger, Chad G. Wilson, Poornima P Sulibele, James Franklin Driftmyer
  • Patent number: 10331576
    Abstract: A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Timothy W. Steele, Gary E. Strait, Poornima P. Sulibele, Guy G. Tracy
  • Publication number: 20180307628
    Abstract: A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.
    Type: Application
    Filed: April 25, 2017
    Publication date: October 25, 2018
    Inventors: Michael A. Blake, Pak-kin Mak, Robert J. Sonnelitter, III, Timothy W. Steele, Gary E. Strait, Poornima P. Sulibele, Guy G. Tracy