Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to preserve privacy in a user dataset including interface circuitry, machine readable instructions, and programmable circuitry to determine a data usage type for each one of a plurality of user data features in a first dataset, classify the data usage type associated with each user data feature of the plurality of user data feature into a feature category, apply at least one feature engineering mechanism to feature categories of the data usage types of the plurality of user data features, select, based on application of feature engineering, a subset of the plurality of user data features for a feature selection training model, and output a second dataset based on the subset of the plurality of user data for the feature selection training model, the second dataset to include fewer user data features than the first dataset.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed that include interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to associate first datapoints of a first feature with a first node, associate second datapoints of a second feature with a second node, construct a graph from the first datapoints and the second datapoints, and perform a comparison of a graph accuracy with a baseline accuracy.

Abstract: An embodiment of an apparatus may comprise a controller coupled to one or more substrates and including circuitry to control access to NVM with a destructive read characteristic, perform a first read of a codeword from the NVM at a first reference voltage of a low confidence zone, perform a second read of the codeword from the NVM at a second reference voltage of the low confidence zone, and assign a lower confidence value to bits of the codeword that have a different value for the first read of the codeword and the second read of the codeword as compared to a confidence value assigned to bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword. Other embodiments are disclosed and claimed.

Abstract: Self-configuring error control coding in a memory device provides flexibility in terms of decoding latency, mis-correct probability, and bit-error rate performance, and avoids labor-intensive trial-and-error configuration of decoding algorithm tuning parameters, such as bit flip algorithm thresholds and syndrome-weight maps. A self-configuring decoder for error control coding allows dynamic trading of error floor performance for error rate performance and vice versa based on the performance characteristics of the decoding process.

Abstract: Self-configuring error control coding in a memory device provides flexibility in terms of decoding latency, mis-correct probability, and bit-error rate performance, and avoids labor-intensive trial-and-error configuration of decoding algorithm tuning parameters, such as bit flip algorithm thresholds and syndrome-weight maps. A self-configuring decoder for error control coding allows dynamic trading of error floor performance for error rate performance and vice versa based on the performance characteristics of the decoding process.