Patents by Inventor Pooya Tadayon

Pooya Tadayon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984430
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug Ingerly
  • Patent number: 11978689
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
  • Patent number: 11976671
    Abstract: Embodiments disclosed herein include temperature control systems. In an embodiment, a temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber, and where the fluid reservoir is between the vacuum source and the spray chamber.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Paul Diglio, Pooya Tadayon, David Shia
  • Publication number: 20240094476
    Abstract: Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Applicant: Intel Corporation
    Inventors: Wesley B. Morgan, David Shia, Mohanraj Prabhugoud, Eric J. M. Moret, Pooya Tadayon
  • Publication number: 20240087971
    Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Brandon C. MARIN, Gang DUAN, Srinivas V. PIETAMBARAM, Kristof DARMAWIKARTA, Jeremy D. ECTON, Suddhasattwa NAD, Hiroki TANAKA, Pooya TADAYON
  • Publication number: 20240063134
    Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and an individual conductive segment may have a conductivity that is close to or less than a conductivity of a conductive line of an individual microstrip.
    Type: Application
    Filed: February 26, 2021
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Xiaoning Ye, Pooya Tadayon, Wenzhi Wang, Srinivasa R. Aravamudhan, Nathan Somnang Tan, Brett Daniel Grossman
  • Publication number: 20240038729
    Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Inventor: Pooya TADAYON
  • Publication number: 20240038722
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Inventors: Mark T. BOHR, Wilfred GOMES, Rajesh KUMAR, Pooya TADAYON, Doug INGERLY
  • Publication number: 20240027698
    Abstract: A photonic device, an integrated circuit device assembly including the photonic device, and a method of fabricating the photonic device. The device includes: a substrate; photonic circuitry on the substrate; an optical waveguide structure on the substrate; an optical coupler coupled to the photonic circuitry at one end thereof by way of the optical waveguide structure, and having a terminus at another end thereof to output an optical beam; and a metalens structure on the substrate, the metalens structure including a plurality of vertical nanostructures to configure an optical path between the optical coupler and an optical interface component that is to be optically coupled to the photonic device.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Nicholas D. Psaila, Pooya Tadayon
  • Publication number: 20240027697
    Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: Wesley B. Morgan, Mohanraj Prabhugoud, David Shia, Eric J. M. Moret, Pooya Tadayon, Tarek A. Ibrahim
  • Publication number: 20240027706
    Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Eric J. M. Moret, Tarek A. Ibrahim, David Shia, Nicholas D. Psaila, Russell Childs
  • Publication number: 20240027699
    Abstract: Technologies for beam expansion in glass substrates are disclosed. In the illustrative embodiment, light in a waveguide defined in a glass substrate is allowed to expand towards a curved mirror defined in the glass substrate. The light is collimated to a beam as it is reflected off the mirror. In the illustrative embodiment, the light is reflected upwards toward the top surface of the glass substrate. A photonic integrated circuit (PIC) die may be mounted on the glass substrate. A micromirror lens fixed to the PIC die can focus the collimated beam into a waveguide defined in the PIC die. In some embodiments, an interface for an optical connector may be formed in the glass substrate, allowing the optical connector to be removably plugged into the glass substrate.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: Nicholas D. Psaila, Pooya Tadayon
  • Patent number: 11822249
    Abstract: Disclosed is a method to develop lithographically defined high aspect ratio interconnects. Also disclosed is an apparatus comprising at least one vessel having a bottom and at least one sidewall extending from the bottom, wherein the at least one sidewall encloses an interior of the at least one vessel, a shaft having a proximal end and a distal end, wherein the distal end of the shaft extends into the interior of the at least one vessel, wherein the proximal end of the shaft is coupled to a motor, at least one support structure which extends laterally from the shaft, and a substrate attachment fixture on a distal end of the at least one support structure, wherein the at least one support structure and the substrate attachment fixture are within the interior of the at least one vessel.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: November 21, 2023
    Assignee: Intel Corporation
    Inventor: Pooya Tadayon
  • Patent number: 11824041
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 21, 2023
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug Ingerly
  • Patent number: 11817423
    Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventor: Pooya Tadayon
  • Patent number: 11774489
    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Patent number: 11756860
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
  • Publication number: 20230260870
    Abstract: Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Inventors: Prabhakar SUBRAHMANYAM, Tewodros WONDIMU, Ying-Feng PANG, Muhammad AHMAD, Paul DIGLIO, David SHIA, Pooya TADAYON
  • Publication number: 20230238357
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Inventors: Mark T. BOHR, Wilfred GOMES, Rajesh KUMAR, Pooya TADAYON, Doug INGERLY
  • Publication number: 20230204819
    Abstract: Technologies for chip-to-chip optical data transfer are disclosed. In the illustrative embodiment, microLEDs on a first chip are used to send data to microphotodiodes on a second chip. The beams from the microLEDs may be sent to the microphotodiodes using an optical bridge, microprisms, a channel through a substrate, a channel defined in a substrate, etc. The microLEDs may be used for high-speed data transfer with low power usage. A chip may include a relatively large number of microLEDs and/or microphotodiodes, allowing for a large bandwidth connection. MicroLEDs and microphotodiodes may be used to connect different parts of the same chip, different chips on the same package, different packages on the same device, or different chips on different devices.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: Khaled Ahmed, Pooya Tadayon, Joshua B. Fryman, Sergey Yuryevich Shumarayev