Abstract: An apparatus is described. The apparatus includes a chip package cooling assembly chamber having one or more features to receive one or more heat pipes that receive heat generated by one or more semiconductor devices that reside outside the chip package. In detail, the heat pipes that are thermally coupled to the VR FET heat sinks are attached to the outside of the cold plate (again, they can be screwed to the cold plate with a thermal interface material between them). Thus, heat generated by the VR FETs is transferred to the VR FET heatsinks and the chip package cold plate via the heat pipes. The heat is then transferred to the fluid while it runs through the cold plate and is removed from the system by the fluid as it exits the outlet.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: An apparatus an apparatus comprising: a substrate having a plane; and an array of at least one conductive probe having a base affixed to the substrate, the at least one conductive probe having a major axis extending from the plane of the substrate and terminating at a tip, wherein the one or more conductive probes comprise at least three points that are non-collinear.

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: Embodiments disclosed herein include temperature control systems. In an embodiment, a temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber, and where the fluid reservoir is between the vacuum source and the spray chamber.

Abstract: Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and an individual conductive segment may have a conductivity that is close to or less than a conductivity of a conductive line of an individual microstrip.

Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: A photonic device, an integrated circuit device assembly including the photonic device, and a method of fabricating the photonic device. The device includes: a substrate; photonic circuitry on the substrate; an optical waveguide structure on the substrate; an optical coupler coupled to the photonic circuitry at one end thereof by way of the optical waveguide structure, and having a terminus at another end thereof to output an optical beam; and a metalens structure on the substrate, the metalens structure including a plurality of vertical nanostructures to configure an optical path between the optical coupler and an optical interface component that is to be optically coupled to the photonic device.

Abstract: Technologies for beam expansion in glass substrates are disclosed. In the illustrative embodiment, light in a waveguide defined in a glass substrate is allowed to expand towards a curved mirror defined in the glass substrate. The light is collimated to a beam as it is reflected off the mirror. In the illustrative embodiment, the light is reflected upwards toward the top surface of the glass substrate. A photonic integrated circuit (PIC) die may be mounted on the glass substrate. A micromirror lens fixed to the PIC die can focus the collimated beam into a waveguide defined in the PIC die. In some embodiments, an interface for an optical connector may be formed in the glass substrate, allowing the optical connector to be removably plugged into the glass substrate.

Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.

Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.

Abstract: Disclosed is a method to develop lithographically defined high aspect ratio interconnects. Also disclosed is an apparatus comprising at least one vessel having a bottom and at least one sidewall extending from the bottom, wherein the at least one sidewall encloses an interior of the at least one vessel, a shaft having a proximal end and a distal end, wherein the distal end of the shaft extends into the interior of the at least one vessel, wherein the proximal end of the shaft is coupled to a motor, at least one support structure which extends laterally from the shaft, and a substrate attachment fixture on a distal end of the at least one support structure, wherein the at least one support structure and the substrate attachment fixture are within the interior of the at least one vessel.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.