Patents by Inventor Pooya Tadayon

Pooya Tadayon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11024601
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug Ingerly
  • Publication number: 20210120703
    Abstract: An apparatus is described. The apparatus includes a liquid cooling system having multiple heat-exchangers and multiple valves. The multiple valves are to enable/disable participation of individual ones of the heat-exchangers within the liquid cooling system. The apparatus includes an information keeping device to store information that correlates a number of the multiple heat exchangers to be enabled to realize one or more semiconductor chips' target temperature for a power consumption of the one or more semiconductor chips for a plurality of combinations of target temperature and power consumption.
    Type: Application
    Filed: December 26, 2020
    Publication date: April 22, 2021
    Inventors: Prabhakar SUBRAHMANYAM, Arun KRISHNAMOORTHY, Victor POLYANKO, Ying-Feng PANG, Yi XIA, Pooya TADAYON, Muhammad AHMAD, Rahima K. MOHAMMED
  • Publication number: 20210088554
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 10935573
    Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Joe Walczyk, Pooya Tadayon
  • Publication number: 20210035951
    Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventor: Pooya TADAYON
  • Publication number: 20210028087
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Shrenik KOTHARI, Chandra Mohan JHA, Weihau TANG, Robert SANKMAN, Xavier BRUN, Pooya TADAYON
  • Publication number: 20200411408
    Abstract: Disclosed embodiments include composite compliant pillars in a micro-structure array that extend at a non-orthogonal angle from a heat-sink base. The array is deployed against an integrated-circuit device package to deflect the composite compliant pillar array under conditions where heat-transfer performance is agnostic to dynamic non-planarity of the integrated-circuit device package.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Joe Walczyk, Pooya Tadayon, Michael Rutigliano, Chandra M. Jha, Zhimin Wan
  • Patent number: 10877068
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 10866264
    Abstract: An interconnect structure is provided which includes: a member having a first end coupled to a test card, and a second end opposite the first end; and a contact tip at the second end of the member, the contact tip to removably attach to another interconnect structure of a device under test, where a modulus of elasticity of the member varies along a length of the member.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Publication number: 20200388603
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Inventors: Robert L. Sankman, Pooya Tadayon, Weihua Tang, Chandra M. Jha, Zhimin Wan
  • Publication number: 20200328139
    Abstract: Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: Chia-Pin CHIU, Robert SANKMAN, Pooya TADAYON
  • Patent number: 10677845
    Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Abram M. Detofsky, Evan M. Fledell, Mustapha A. Abdulai, John M. Peterson, Dinia P. Kitendaugh, Pooya Tadayon, Jin Pan, David Shia
  • Publication number: 20200103440
    Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Joe Walczyk, Pooya Tadayon
  • Publication number: 20200096567
    Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
  • Publication number: 20200098666
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: INTEL CORPORATION
    Inventors: ZHIMIN WAN, CHIA-PIN CHIU, POOYA TADAYON, JOE F. WALCZYK, CHANDRA MOHAN JHA, WEIHUA TANG, SHRENIK KOTHARI, SHANKAR DEVASENATHIPATHY
  • Publication number: 20200072871
    Abstract: Space transformation technology for probe cards at sort is disclosed. In one example, a space transformer transforms a pitch of electrical contacts from a first distribution to a second distribution. The space transformer comprises a substrate with opposite first and second sides; and vias extending through the substrate between the first and second sides and oriented at different angles with respect to one another. In one example, a tester system or probe card for a die comprises a printed circuit board (PCB) with pads having a pad pitch; and a space transformer operatively coupled to the PCB, and having vias extending from the pads of the PCB through the space transformer at different angles with respect to one another and configured to electrically connect to contacts on the die having a contact pitch different than the pad pitch.
    Type: Application
    Filed: March 31, 2017
    Publication date: March 5, 2020
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Joe F. Walczyk, Keith J. Marting
  • Publication number: 20200066679
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Application
    Filed: December 21, 2017
    Publication date: February 27, 2020
    Inventors: Mark T. BOHR, Wilfred GOMES, Rajesh KUMAR, Pooya TADAYON, Doug INGERLY
  • Publication number: 20200025801
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Publication number: 20190385925
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Joe F. Walczyk, Pooya Tadayon
  • Patent number: 10488438
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk