Patents by Inventor Poras T. Balsara

Poras T. Balsara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9369041
    Abstract: A voltage converter for converting an input voltage to an output voltage is disclosed. The voltage converter includes a voltage converter circuit having a set of switches, a switch driver connected to the voltage converter circuit, a controller connected to the switch driver and the output voltage, a target output voltage connected to the controller, a control signal generated by the controller for the switch driver that includes a duty ratio based on the target output voltage and the output voltage. The switch driver is configured to apply the control signal to the set of switches and the voltage converter circuit generates the output voltage based on the duty ratio to match the target output voltage.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 14, 2016
    Assignees: Cirasys, Inc., The Board of Regents, The University of Texas System
    Inventors: Vikas V. Paduvalli, Louis R. Hunt, Poras T. Balsara, Robert J. Taylor
  • Publication number: 20140361754
    Abstract: A voltage converter for converting an input voltage to an output voltage is disclosed. The voltage converter includes a voltage converter circuit having a set of switches, a switch driver connected to the voltage converter circuit, a controller connected to the switch driver and the output voltage, a target output voltage connected to the controller, a control signal generated by the controller for the switch driver that includes a duty ratio based on the target output voltage and the output voltage. The switch driver is configured to apply the control signal to the set of switches and the voltage converter circuit generates the output voltage based on the duty ratio to match the target output voltage.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 11, 2014
    Applicants: Cirasys, Inc., The Board of Regents, The University of Texas System
    Inventors: Vikas V. Paduvalli, Louis R. Hunt, Poras T. Balsara, Robert J. Taylor
  • Patent number: 8803498
    Abstract: An apparatus and method is presented for implementing and controlling a voltage converter with one input voltage and multiple output voltages. In the case of boost and buck-boost converters, a converter circuit with one inductor and a switched group of parallel connection capacitors is realized, one parallel connection for each output voltage. A duty ratio is monitored for the inductor and the switched group of capacitors to provide a set of duty ratios. The duty ratios form a control vector which describes the control inputs. The output voltages are the control outputs describing a MIMO system. A generalized Cuk-Middlebrook modeling approach is applied to the voltage converter, along with linearization and MIMO control methods to regulate all output voltages to desired levels.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: August 12, 2014
    Assignees: Cirasys, Inc., Board of Regents, The University of Texas System
    Inventors: Louis Roberts Hunt, Dinesh Kumar Bhatia, Poras T. Balsara
  • Patent number: 8260279
    Abstract: The present invention provides a software defined radio transceiver that includes a programmable cellular radio front end and a programmable baseband processor. The programmable cellular radio front end is typically a digital radio frequency processor configured to support a cellular communication standard. The programmable baseband processor is connected to the digital radio frequency processor.
    Type: Grant
    Filed: November 15, 2009
    Date of Patent: September 4, 2012
    Assignee: Board of Regents, The University of Texas System
    Inventors: Kamran Kiasaleh, Poras T. Balsara
  • Publication number: 20120139509
    Abstract: An apparatus and method is presented for implementing and controlling a voltage converter with one input voltage and multiple output voltages. In the case of boost and buck-boost converters, a converter circuit with one inductor and a switched group of parallel connection capacitors is realized, one parallel connection for each output voltage. A duty ratio is monitored for the inductor and the switched group of capacitors to provide a set of duty ratios. The duty ratios form a control vector which describes the control inputs. The output voltages are the control outputs describing a MIMO system. A generalized Cuk-Middlebrook modeling approach is applied to the voltage converter, along with linearization and MIMO control methods to regulate all output voltages to desired levels.
    Type: Application
    Filed: November 22, 2011
    Publication date: June 7, 2012
    Inventors: Louis Roberts Hunt, Dinesh Kumar Bhatia, Poras T. Balsara
  • Publication number: 20100144333
    Abstract: The present invention provides a software defined radio transceiver that includes a programmable cellular radio front end and a programmable baseband processor. The programmable cellular radio front end is typically a digital radio frequency processor configured to support a cellular communication standard. The programmable baseband processor is connected to the digital radio frequency processor.
    Type: Application
    Filed: November 15, 2009
    Publication date: June 10, 2010
    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Kamran Kiasaleh, Poras T. Balsara
  • Patent number: 6130559
    Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 10, 2000
    Assignee: Board of Regents of the University of Texas System
    Inventors: Poras T. Balsara, Kamal J. Koshy