Patents by Inventor Porter B. Click, Jr.

Porter B. Click, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5665649
    Abstract: A method of manufacturing semiconductor devices is disclosed which incorporates an array of bases formed on a plastic sheet. Each base in the array includes individual leads used to connect the semiconductor die to an external circuit. To keep the plastic sheet from flexing during assembly the plastic sheet is placed between a foundation and an anchor grid, where the foundation provides a rigid platform for the plastic sheet and the anchor grid hold the sheet to the foundation. Once the semiconductor dies have been attached to the bases, a protective cap is placed over the die. An adhesive sheet is then place over all the caps in the array allowing the array to be milled to separate the individual packages without scattering the devices.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: September 9, 1997
    Assignee: Gardiner Communications Corporation
    Inventors: James Marvin Harris, Brigitte Ursula Kiba, Porter B. Click, Jr.
  • Patent number: 5596171
    Abstract: A package for a semiconductor die, particularly field effect transistors, operating at very high frequencies includes a base having integrally formed conductor supports. The base and the supports are formed from a thermo-formed or thermo-set plastic material. Metal conductors are plated to the supports and terminate in pads for connecting the die to an external circuit. A die is attached to the base and wires bonded to the package conductor pads. The surface of the die, the bond wires and the surface of the package conductors are substantially coplanar to reduce abrupt changes in the path of signal flow which reduces radiation losses. Package dimensions and conductor proximities and bond wire lengths are precisely located and enhanced to reduce parasitic inductances. When connected to an external circuit, the package is flipped and its lid inserted into a hole in the circuit board. The package conductors rest against the circuit board to the semiconductor device.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: January 21, 1997
    Inventors: James M. Harris, Brigitte U. Kiba, Porter B. Click, Jr.