Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.

Abstract: An optical imaging lens assembly includes seven lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The second lens element has negative refractive power. The object-side surface of the third lens element is concave in a paraxial region thereof. The fourth lens element has positive refractive power. The image-side surface of the fifth lens element is concave in a paraxial region thereof. The sixth lens element has positive refractive power, and the image-side surface of the sixth lens element is convex in a paraxial region thereof.

Abstract: A method for calculating state of health of battery, performed by a processing control circuit, includes: charging a battery under test to an upper voltage with a first constant current through a charging circuit and an electrical measuring circuit, discharging the battery under test to a lower voltage with a second constant current through the charging circuit and the electrical measuring circuit, obtaining an accumulated discharge capacity from the upper voltage to the lower voltage through the electrical measuring circuit, and calculating a state of health of the battery under test at least according to the accumulated discharge capacity and a design capacity.

Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Abstract: An optical photographing lens assembly includes six lens elements which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, and a sixth lens element. Each of the six lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The fourth lens element has positive refractive power. The image-side surface of the fourth lens element is convex in a paraxial region thereof. The image-side surface of the fifth lens element is concave in a paraxial region thereof. The sixth lens element has negative refractive power. The object-side surface of the sixth lens element is convex in a paraxial region thereof.

Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Abstract: A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas: Tx > Dx - Sx ; ? Tx < Dx - Sx + Wx ? 2 ; ? Tx > Sx ; ? Tx < Dx - Sx + Wx ? 1 ; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.

Abstract: A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas: Tx>Dx?Sx; Tx<Dx?Sx+Wx2; Tx>Sx; Tx<Dx?Sx+Wx1; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.

Abstract: A photographing system lens assembly includes, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one surface of at least one lens element in the photographing system lens assembly has at least one inflection point. The first lens element has positive refractive power, the object-side surface of the first lens element is convex in a paraxial region thereof, and the image-side surface of the first lens element is convex in a paraxial region thereof. The object-side surface of the second lens element is concave in a paraxial region thereof. The image-side surface of the third lens element is concave in a paraxial region thereof.

Abstract: A method for calculating state of health of battery, performed by a processing control circuit, includes: charging a battery under test to an upper voltage with a first constant current through a charging circuit and an electrical measuring circuit, discharging the battery under test to a lower voltage with a second constant current through the charging circuit and the electrical measuring circuit, obtaining an accumulated discharge capacity from the upper voltage to the lower voltage through the electrical measuring circuit, and calculating a state of health of the battery under test at least according to the accumulated discharge capacity and a design capacity.

Abstract: A dynamic calibration method for heterogeneous sensors includes: sensing dynamic objects by a first sensor to generate first sensing data; sensing the dynamic objects by a second sensor to generate second sensing data; performing feature matching between the first sensing data and the second sensing data to determine first valid data and second valid data, and identifying a tracked object from the dynamic objects based on the first valid data and the second valid data; performing feature comparison between the first valid data and the second valid data corresponding to the tracked object to calculate data errors between the first sensor and the second sensor; and calculating a calibration parameter based on the first valid data and the second valid data when the number of the data errors exceeds an error threshold, and adjusting the first sensing data and the second sensing data based on the calibration parameter.

Abstract: A method and an apparatus for computation on a convolutional layer of a neural network are proposed. The apparatus includes an adder configured to receive a first sum of products, receive a pre-computed convolution bias of the convolutional layer, and perform accumulation on the first sum of products and the pre-computed convolution bias to generate an adder result of the convolutional layer, where the first sum of products is a sum of products of quantized input activation of the convolutional layer and quantized convolution weights of the convolutional layer, and where the pre-computed convolution bias is associated with a zero point of input activation of the convolutional layer and a zero point of output activation of the convolutional layer.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a nitride-based layer, and a plurality of gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The nitride-based layer is disposed over the second nitride-based semiconductor layer and extends along a first direction to have a strip profile. The gate electrodes are disposed over the nitride-based layer and arranged along the first direction such that at least two of the gate electrodes are separated from each other.

Abstract: The disclosure provides an image processing device. An image processing device includes a neural network circuit, a gain control circuit, and an image merge circuit. The neural network circuit is configured to receive an input image, and perform an image processing operation on the input image according to fixed parameters to output a first intermediate image. The gain control circuit, coupled to the neural network circuit, is configured to receive the first intermediate image from the neural network circuit, and multiply the first intermediate image by at least one amplitude gain to output a second intermediate image. The image merge circuit, coupled to the gain control circuit, configured to receive the second intermediate image and the input image, and combine the second intermediate image and the input image to obtain an output image. In addition, a method for image enhancement is also provided.

Abstract: A convolutional neural network (CNN) operation accelerator comprising a first sub-accelerator and a second sub-accelerator is provided. The first sub-accelerator comprises I units of CNN processor cores, J units of element-wise & quantize processors, and K units of pool and nonlinear function processor. The second sub-accelerator comprises X units of CNN processor cores, Y units of first element-wise & quantize processors, and Z units of pool and nonlinear function processor. The above variables I˜K, X˜Z are all greater than 0, and at least one of the three relations, namely, “I is different from X”, “J is different from Y”, and “K is different from Z”, is satisfied. A to-be-performed CNN operation comprises a first partial CNN operation and a second partial CNN operation. The first sub-accelerator and the second sub-accelerator perform the first partial CNN operation and the second partial CNN operation, respectively.

Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Abstract: A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas: Tx>Dx?Sx; Tx<Dx?Sx+Wx2; Tx>Sx; Tx<Dx?Sx+Wx1; wherein, Tx represents a searching distance for finding an end-point of the first portion or an end-point of the first part; and Sx represents an actual shifting amount of the first portion.

Abstract: The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.

Abstract: The disclosure provides an image processing device. An image processing device includes a neural network circuit, a gain control circuit, and an image merge circuit. The neural network circuit is configured to receive an input image, and perform an image processing operation on the input image according to fixed parameters to output a first intermediate image. The gain control circuit, coupled to the neural network circuit, is configured to receive the first intermediate image from the neural network circuit, and multiply the first intermediate image by at least one amplitude gain to output a second intermediate image. The image merge circuit, coupled to the gain control circuit, configured to receive the second intermediate image and the input image, and combine the second intermediate image and the input image to obtain an output image. In addition, a method for image enhancement is also provided.

Abstract: A verification system and a verification method for a neural network accelerator hardware are provided. The verification system for a neural network accelerator hardware includes a neural network graph compiler and an execution performance estimator. The neural network graph compiler is configured to receive an assumed neural network graph and convert the assumed neural network graph into a suggested inference neural network graph according to a hardware information and an operation mode. The execution performance estimator is configured to receive the suggested inference neural network graph and calculate an estimated performance of the neural network accelerator hardware according to a hardware calculation abstract information of the suggested inference neural network graph.