Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

Abstract: A power stage in a multi-phase switching power supply incorporates a current sense circuit coupled to the output voltage disconnect transistor to conduct a portion of an inductor current flowing in the output inductor of the power stage. The current sense circuit is controlled by the same control signal controlling the output voltage disconnect transistor. The portion of the inductor current being conducted by the current sense circuit includes an upslope current and a downslope current of the inductor current. A phase redundant controller generates a sense current signal indicative of the portion of the inductor current conducted by the current sense circuit. Accurate current sensing is implemented for the power stage where the current sense value dose not require temperature compensation.

Abstract: A power stage in a multi-phase switching power supply incorporates a current sense circuit coupled to the output voltage disconnect transistor to conduct a portion of an inductor current flowing in the output inductor of the power stage. The current sense circuit is controlled by the same control signal controlling the output voltage disconnect transistor. The portion of the inductor current being conducted by the current sense circuit includes an upslope current and a downslope current of the inductor current. A phase redundant controller generates a sense current signal indicative of the portion of the inductor current conducted by the current sense circuit. Accurate current sensing is implemented for the power stage where the current sense value dose not require temperature compensation.

Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

Abstract: A power stage in a multi-phase switching power supply incorporates a current sense transistor coupled in series with the output inductor to sense the phase current for the power stage. In some embodiments, the current sense transistor mirrors the output voltage disconnect transistor (the ORing FET) used to switchably connect a power stage to the output voltage node. The current sense transistor measures a portion of the inductor current flowing through the output inductor where the inductor current is indicative of the phase current of the power stage. Accurate current sensing is implemented for the power stage where the current sense value dose not require temperature compensation.

Abstract: A power stage in a multi-phase switching power supply incorporates a current sense transistor coupled in series with the output inductor to sense the phase current for the power stage. In some embodiments, the current sense transistor mirrors the output voltage disconnect transistor (the ORing FET) used to switchably connect a power stage to the output voltage node. The current sense transistor measures a portion of the inductor current flowing through the output inductor where the inductor current is indicative of the phase current of the power stage. Accurate current sensing is implemented for the power stage where the current sense value dose not require temperature compensation.

Abstract: A method, system and computer program product for improving inductor current ramp down times in a DC-to-DC converter having an inductor conductively coupled to a low side transistor on a first side and an or-ing transistor coupled to a second side, where the DC-to-DC converter is in a phase redundant power supply. The method comprises turning off the low side transistor and turning off the or-ing transistor in response to an unloading transient.

Abstract: Apparatus and associated methods relate to copying a pulse-width-modulated (PWM) signal PWMin to N-1 delay controllers to form N-1 time-interleaved PWM signals. In an illustrative example, each of the N-1 delay controllers may set and reset a corresponding latch to form leading and/or trailing edges of a corresponding generated PWM signal (PWM2 to PWMN) in response to a copied PWM signal and/or a phase-shifted clock. In some examples, the delay controller may fine tune the pulse width of any of the generated PWM signals (PWM2 to PWMN) to correct phase current balance supplied to a load. The phase multiplier may advantageously split one PWM signal supplied by a PWM controller, for example, into multiple interleaved PWM phase signals without expanding the number of PWM signal pins on the PWM controller.

Abstract: A method, system and computer program product for improving inductor current ramp down times in a DC-to-DC converter having an inductor conductively coupled to a low side transistor on a first side and an or-ing transistor coupled to a second side, where the DC-to-DC converter is in a phase redundant power supply. The method comprises turning off the low side transistor and turning off the or-ing transistor in response to an unloading transient.