Abstract: A computer-implemented method of mapping attribute names of a source data model to a destination data model includes processing one or more source attribute names from the source data model and one or more destination attribute names of the destination data model to obtain standardized attribute names. The method includes determining whether any of the source attribute names have an existing entry in a custom dictionary. The method includes, for each source attribute name that has an existing entry in the custom dictionary, recording an output mapping for the source attribute name according to the existing entry in the custom dictionary. The method includes, for each source attribute name that does not have an existing entry in the custom dictionary, using a machine learning model to predict the mapping of each source attribute name to a corresponding one of the destination attribute names.

Abstract: A computer-implemented method of mapping attribute names of a source data model to a destination data model includes processing one or more source attribute names from the source data model and one or more destination attribute names of the destination data model to obtain standardized attribute names. The method includes determining whether any of the source attribute names have an existing entry in a custom dictionary. The method includes, for each source attribute name that has an existing entry in the custom dictionary, recording an output mapping for the source attribute name according to the existing entry in the custom dictionary. The method includes, for each source attribute name that does not have an existing entry in the custom dictionary, using a machine learning model to predict the mapping of each source attribute name to a corresponding one of the destination attribute names.

Abstract: A computer-implemented method of mapping attribute names of a source data model to a destination data model includes obtaining multiple source attribute names from the source data model, and obtaining multiple destination attribute names from the destination data model. The destination data model includes multiple attributes that correspond to attributes in the source data model having different attribute names. The method includes processing the obtained source attribute names and the obtained destination attribute names to standardize the attribute names according to specified character formatting, supplying the standardized attribute names to a machine learning network model to predict a mapping of each source attribute name to a corresponding one of the destination attribute names, and outputting, according to mapping results of the machine learning network model, an attribute mapping table indicating the predicted destination attribute name corresponding to each source attribute name.

Abstract: Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package.

Abstract: Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package.

Abstract: One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out.

Abstract: A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.