Abstract: A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.

Abstract: A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.

Abstract: A fail-safe booting system suitable for a system-on-chip (SOC) automatically detects and rectifies failures in power-on reset (POR) configuration or boot loader fetch operations. If a failure due to a boot loader fetch occurs, a POR configuration and boot loader are fetched from a different non-volatile memory. The reloading takes place from further different non-volatile memory sources if the boot loader fetch fails again. The automated system operates in accordance with a state machine, and does not involve any manual, on-board switch selection or manual re-programming.

Abstract: A fail-safe booting system suitable for a system-on-chip (SOC) automatically detects and rectifies failures in power-on reset (POR) configuration or boot loader fetch operations. If a failure due to a boot loader fetch occurs, a POR configuration and boot loader are fetched from a different non-volatile memory. The reloading takes place from further different non-volatile memory sources if the boot loader fetch fails again. The automated system operates in accordance with a state machine, and does not involve any manual, on-board switch selection or manual re-programming.