Abstract: An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records.

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.

Abstract: An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records.

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.

Abstract: A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.

Abstract: A differential cascode voltage switch circuit includes a plurality of devices wherein a portion of the plurality of devices have a low threshold voltage and a remainder of the plurality devices have a regular threshold voltage for providing a performance gain without a substantial increase in standby power wherein at least one device has regular threshold voltage between a supply voltage and a ground. A method of producing a multi-threshold voltage circuit includes the steps of defining between a supply voltage node and ground at least one regular threshold voltage device for producing a high resistance to reduce current leakage and defining low threshold voltage devices within the circuit for reducing leakage current.